Power converter

US10103640B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10103640-B2
Application numberUS-201514624238-A
CountryUS
Kind codeB2
Filing dateFeb 17, 2015
Priority dateFeb 20, 2014
Publication dateOct 16, 2018
Grant dateOct 16, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A power converter, including: at least two inverting modules, where direct current sides of the at least two inverting modules are connected in parallel using a laminated busbar or a circuit board, and the at least two inverting modules run in an interleaved and parallel manner. In the present invention, the power converter is formed by connecting at least two inverting modules in parallel, and the direct current sides of the at least two inverting modules are connected in parallel using the laminated busbar or the circuit board, so that parasitic inductance between inverting modules is small, forming a low parasitic inductance loop. When the at least two inverting modules run in an interleaved and parallel manner, the low parasitic inductance loop counteracts most ripple currents in a circuit, thereby reducing the burden of the ripple currents on a bus capacitor. Therefore, the demand of the power converter provided in the present invention for the bus capacitor is small.

First claim

Opening claim text (preview).

What is claimed is: 1. A power converter, comprising: two inverters running in parallel in an interleaved manner, each inverter comprising: an inverter positive port; an inverter negative port; an N-pole port; an alternating current side connected to the alternating current side of the other inverter; and a direct current side connected in parallel to the direct current side of the other inverter using a circuit board, the circuit board comprising at least two circuit board conducting layers and a circuit board insulation layer, the circuit board conducting layers comprising an N-pole circuit board conducting layer coupled to the N-pole port, the circuit board insulation layer disposed between two of the circuit board conducting layers, each of the circuit board conducting layers comprising: a positive circuit board conducting layer coupled to the inverter positive ports and configured to couple to a direct current power supply positive port; and a negative circuit board conducting layer coupled to the inverter negative ports and configured to couple to a direct current power supply negative port. 2. The power converter of claim 1 , wherein a number of circuit board conducting layers located between the positive circuit board conducting layer and the negative circuit board conducting layer is less than or equal to seven. 3. The power converter of claim 1 , wherein the inverters comprise a three-phase inverter. 4. The power converter of claim 3 , wherein the three-phase inverter comprises a three-phase inverter formed by combining single-phase inverters. 5. The power converter of claim 1 , wherein the inverters comprise a single-phase inverter. 6. The power converter of claim 1 , wherein the inverters comprise a multi-level inverter. 7. The power converter of claim 1 , wherein a working current of the power converter is less than or equal to 300 amperes (A). 8. The power converter of claim 1 , wherein the circuit board conducting layers comprise a copper layer. 9. The power converter of claim 1 , wherein a number of circuit board conducting layers is at least three, the circuit board conducting layers further comprise an N-pole circuit board conducting layer configured to connect to an N-pole port of the inverters, a distance between the N-pole circuit board conducting layer and the positive circuit board conducting layer is less than or equal to 15 millimeters (mm), a distance between the positive circuit board conducting layer and the negative circuit board conducting layer is less than or equal to 15 mm, and the number of circuit board conducting layers located between the N-pole circuit board conducting layer and the negative circuit board conducting layer is less than or equal to seven. 10. A power converter, comprising: two inverters running in parallel in an interleaved manner, each inverter comprising: an N-pole port; an alternating current side connected to the alternating current side of the other inverter; and a direct current side connected in parallel to the direct current side of the other inverter using a circuit board, the circuit board comprising at least three circuit board conducting layers and a circuit board insulation layer, the circuit board insulation layer disposed between two of the circuit board conducting layers and comprising an N-pole circuit board conducting layer coupled to the N-pole port. 11. The power converter of claim 10 , wherein each of the inverters further comprises an inverter positive port and an inverter negative port, and each of the circuit board conducting layers comprises: a positive circuit board conducting layer coupled to the inverter positive ports and configured to couple to a direct current power supply positive port; and a negative circuit board conducting layer coupled to the inverter negative ports and configured to couple to a direct current power supply negative port, a distance between the positive circuit board conducting layer and the negative circuit board conducting layer being less than or equal to 15 millimeters (mm). 12. The power converter of claim 10 , wherein a number of circuit board conducting layers is at least three, the circuit board conducting layers further comprise an N-pole circuit board conducting layer configured to connect to an N-pole port of the inverters, the number of circuit board conducting layers located between the N-pole circuit board conducting layer and the positive circuit board conducting layer is less than or equal to seven, and the number of circuit board conducting layers located between the N-pole circuit board conducting layer and the negative circuit board conducting layer is less than or equal to seven. 13. The power converter of claim 10 , wherein a working current of the power converter is less than or equal to 300 amperes (A). 14. The power converter of claim 10 , wherein a number of circuit board conducting layers is at least three, the circuit board conducting layers further comprise an N-pole circuit board conducting layer configured to connect to an N-pole port of the inverters, a distance between the N-pole circuit board conducting layer and the positive circuit board conducting layer is less than or equal to 15 millimeters (mm), a distance between the positive circuit board conducting layer and the negative circuit board conducting layer is less than or equal to 15 mm, and the number of circuit board conducting layers located between the N-pole circuit board conducting layer and the negative circuit board conducting layer is less than or equal to seven. 15. A power converter, comprising: two inverters running in parallel in an interleaved manner, each inverter comprising: an N-pole port; an alternating current side connected to the alternating current side of the other inverter; and a direct current side connected in parallel to the direct current side of the other inverter using a laminated busbar, the laminated busbar comprising at least three laminated busbar conducting layers and a laminated busbar insulation layer, the laminated busbar insulation layer disposed between two of the laminated busbar conducting layers and comprising an N-pole laminated busbar conducting layer coupled to the N-pole port. 16. The power converter of claim 15 , wherein each of the inverters further comprises an inverter positive port and an inverter negative port, and each of the laminated busbar conducting layers comprises: a positive laminated busbar conducting layer coupled to the inverter positive ports and configured to couple to a direct current power supply positive port; and a negative laminated busbar conducting layer coupled to the inverter negative ports and configured to couple to a direct current power supply negative port, a distance between the positive laminated busbar conducting layer and the negative laminated busbar conducting layer being less than or equal to 15 millimeters (mm). 17. The power converter of claim 15 , wherein a number of laminated busbar conducting layers is at least three, the laminated busbar conducting layers further comprise an N-pole laminated busbar conducting layer configured to connect to an N-pole port of the inverters, the number of laminated busbar conducting layers located between the N-pole laminated busbar conducting layer and the positive laminated busbar conducting layer is less than or equal to seven, and the number of laminated busbar conducting layers located between the N-pole laminated busbar conducting layer and the negative laminated busbar conducting layer is less than or equal to seven. 18.

Assignees

Inventors

Classifications

  • Housings · CPC title

  • Totally-enclosed installations, e.g. in metal casings · CPC title

  • using semiconductor devices only, e.g. single switched pulse inverters · CPC title

  • Cross-Sectional Technologies · mapped topic

  • H02M7/003Primary

    Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title

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Frequently asked questions

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What does patent US10103640B2 cover?
A power converter, including: at least two inverting modules, where direct current sides of the at least two inverting modules are connected in parallel using a laminated busbar or a circuit board, and the at least two inverting modules run in an interleaved and parallel manner. In the present invention, the power converter is formed by connecting at least two inverting modules in parallel, and…
Who is the assignee on this patent?
Huawei Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H02M7/003. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 16 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).