High reliability etched-facet photonic devices

US10103518B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10103518-B2
Application numberUS-201414296180-A
CountryUS
Kind codeB2
Filing dateJun 4, 2014
Priority dateFeb 18, 2005
Publication dateOct 16, 2018
Grant dateOct 16, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Semiconductor photonic device surfaces are covered with a dielectric or a metal protective layer. The protective layer covers the entire device, including regions near facets at active regions, to prevent bare or unprotected semiconductor regions, thereby to form a very high reliability etched facet photonic device.

First claim

Opening claim text (preview).

What is claimed is: 1. A packaged photonic device, comprising: a substrate; a semiconductor structure on said substrate, said semiconductor structure comprising: an active layer; and etched end facets and etched side walls defining all side surfaces of said semiconductor structure comprising said active layer, wherein said side surfaces are formed on a first portion of said semiconductor structure including said active layer, and wherein a second portion of said semiconductor structure extends laterally beyond each of said side surfaces; a protective layer of a combination of a dielectric material and an electrically conductive material covering all surfaces of said semiconductor structure including: a single continuous layer of a dielectric material directly covering said etched end facets and each of said etched side walls and a first portion of a top surface of said semiconductor structure above said active layer, wherein said active layer extends to said etched end facets and each of said etched side walls, and wherein said single continuous layer of dielectric material directly covers said active layer at said etched end facets and each of said etched side walls to seal said etched end facets and each of said etched side walls; and a single continuous layer of an electrically conductive material directly covering a remaining portion of said top surface of said semiconductor structure only above said active layer, wherein said single continuous layer of electrically conductive material directly overlaps said single continuous layer of dielectric material to seal said top surface of said semiconductor structure; a package containing at least said substrate, said semiconductor structure, and said protective layer. 2. The packaged photonic device of claim 1 , wherein said packaged photonic device is a laser. 3. The packaged photonic device of claim 2 , wherein said laser is a ridge laser comprising a ridge having a top surface and a plurality of side surfaces and a contact window disposed at said ridge top surface, and wherein said single continuous layer of dielectric material completely covers each of said ridge top and side surfaces except for said contact window. 4. The packaged photonic device of claim 1 , wherein said packaged photonic device is an electroabsorption modulator. 5. The packaged photonic device of claim 1 , wherein said packaged photonic device is a semiconductor optical amplifier. 6. The packaged photonic device of claim 1 , wherein said substrate is formed of one of: InP; GaAs; and GaN. 7. The packaged photonic device of claim 1 , wherein said dielectric material is silicon dioxide. 8. The packaged photonic device of claim 1 , wherein said substrate has a singulation edge no less than about 750 nm from said etched end facets and said etched side walls, and wherein said single continuous layer of dielectric material completely covers said substrate between said etched end facets and said etched side walls and said singulation edge. 9. The packaged photonic device of claim 1 , wherein said single continuous layer of dielectric material completely covers a top surface of a portion of said semiconductor structure that extends laterally beyond said side surfaces below said active layer. 10. The packaged photonic device of claim 1 , wherein said semiconductor structure further comprises: a cladding region located below said active layer. 11. The packaged photonic device of claim 10 , further comprising: a second cladding region located above said active layer. 12. The packaged photonic device of claim 11 , further comprising: a cap layer located above said second cladding region; and a contact window defined by said single continuous layer of dielectric material on said top surface of said semiconductor structure, said contact window exposing at least a portion of said cap layer on said top surface of said semiconductor structure. 13. The packaged photonic device of claim 12 , wherein said single continuous layer of electrically conductive material is formed at least in part on said exposed portion of said cap layer. 14. The packaged photonic device of claim 13 , wherein said single continuous layer of electrically conductive material completely covers said contact window and directly overlaps said single continuous layer of dielectric material to completely seal said contact window. 15. The packaged photonic device of claim 12 , wherein said contact window is spaced away from and does not extend to said side surfaces of said semiconductor structure. 16. The packaged photonic device of claim 1 , further comprising: an electrically conductive contact formed on a bottom surface of said substrate opposite said semiconductor structure. 17. The packaged photonic device of claim 1 , wherein said protective layer comprises a single continuous layer of deposited dielectric material. 18. The packaged photonic device of claim 17 , wherein said single continuous layer of deposited dielectric material also extends over said substrate and covers all surfaces of said substrate within 750 nm of said etched end facets and said etched side walls. 19. The packaged photonic device of claim 1 , wherein said single continuous layer of electrically conductive material forms an electrically conductive contact for said packaged photonic device.

Assignees

Inventors

Classifications

  • Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth · CPC title

  • having a ridge or stripe structure · CPC title

  • Etching · CPC title

  • H01S5/323Primary

    in AIIIBV compounds, e.g. AlGaAs-laser, {InP-based laser} · CPC title

  • Window-type lasers, i.e. with a region of non-absorbing material between the active region and the reflecting surface (H01S5/14 takes precedence) · CPC title

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Frequently asked questions

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What does patent US10103518B2 cover?
Semiconductor photonic device surfaces are covered with a dielectric or a metal protective layer. The protective layer covers the entire device, including regions near facets at active regions, to prevent bare or unprotected semiconductor regions, thereby to form a very high reliability etched facet photonic device.
Who is the assignee on this patent?
Macom Tech Solutions Holdings Inc
What technology area does this patent fall under?
Primary CPC classification H01S5/323. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 16 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).