Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode

Patent metadata

Field	Value
Publication number	US-10103240-B2
Application number	US-201313763675-A
Country	US
Kind code	B2
Filing date	Feb 10, 2013
Priority date	Apr 30, 2010
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

First claim

We claim:

1. A method of forming a semiconductor power device comprising:
forming an intermediate semiconductor layer of a second conductivity type on top of a bottom semiconductor layer of a first conductivity type, followed by forming a super junction structure on top of the intermediate semiconductor layer by forming laterally-extended stacking layers of alternating conductivity types of a first and second conductivity type;
forming a gate column of a second conductivity type extending downwardly through the super junction structure;
forming a source column and a drain column of a first conductivity type extending vertically on two opposite sides of the laterally-extended stacking layers with the drain column extending through the super junction structure and electrically connected to the bottom semiconductor layer.

2. The method of claim 1 wherein:
the step of forming the superjunction structure further comprises a step of forming said laterally-extended stacking layers by epitaxial growth on top of said intermediate semiconductor layer.

3. The method of forming a semiconductor device of claim 1 wherein:
the step of forming the gate column further comprising a step of forming the gate column in a trench extending downwardly near a bottom of the intermediate semiconductor layer to form a built-in gate-drain avalanche clamp diode.

4. The method of claim 1 wherein:
the step of forming the source column is a step of forming the source column extending downwardly below the superjunction structure to reach the intermediate semiconductor layer for further forming a bipolar suppression region of a second conductivity type in the intermediate semiconductor layer at the bottom of the source column.

5. The method of claim 1 wherein:
the step of forming said source, drain or gate columns further comprising a step of etching a trench in the semiconductor substrate followed by lining trench walls of the trench with a semiconductor material of the first or second conductivity type.

6. The method of claim 5 wherein:
the step of lining the trench walls further comprises a step of doping exposed portions of the semiconductor substrate along the trench walls.

7. The method of claim 5 wherein:
the step of lining the trench walls further comprises a step of depositing polysilicon of the first or second conductivity type on the trench walls.

8. The method of claim 5 further comprising:
filling the trenches with a dielectric semiconductor material after lining the trench walls.

9. The method of 1 further comprising:
configuring the source, gate and drain columns to function as a JFET; and
forming a MOSFET in the semiconductor substrate as a cascode circuit on the semiconductor substrate with the JFET.

Assignees

• Bobde Madhur
• Guann Lingpeng
• Bhalla Anup
• Yilmaz Hamza
• Alpha & Omega Semiconductor

Inventors

• Bobde Madhur
• Guann Lingpeng
• Bhalla Anup
• Yilmaz Hamza

Classifications

• H01L29/66484 Primary

  Electricity · mapped topic

• H01L29/66909

  Electricity · mapped topic

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D64/411

  for FETs · CPC title