Methods of forming buried junction devices in silicon carbide using ion implant channeling and silicon carbide devices including buried junctions

Patent metadata

Field	Value
Publication number	US-10103230-B2
Application number	US-201615339178-A
Country	US
Kind code	B2
Filing date	Oct 31, 2016
Priority date	Jul 26, 2013
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A semiconductor device structure according to some embodiments includes a silicon carbide substrate having a first conductivity type, a silicon carbide drift layer having the first conductivity type on the silicon carbide substrate and having an upper surface opposite the silicon carbide substrate, and a buried junction structure in the silicon carbide drift layer. The buried junction structure has a second conductivity type opposite the first conductivity type and has a junction depth that is greater than about one micron.

First claim

That which is claimed is:

1. A semiconductor device, comprising:
a silicon carbide substrate having a first conductivity type;
a silicon carbide drift layer having the first conductivity type on the silicon carbide substrate and having an upper surface opposite the silicon carbide substrate; and
a buried junction structure in the silicon carbide drift layer, wherein the buried junction structure comprises floating regions having a second conductivity type opposite the first conductivity type;
wherein the buried junction structure comprises a first buried junction structure having a first junction depth, and wherein the semiconductor device further comprises a second buried junction structure having a second junction depth that is greater than the first junction depth; and
wherein a distance between the first buried junction structure and the second buried junction structure is about 0.1 micron to about 3 microns.

2. The semiconductor device of claim 1 , wherein the first and second buried junction structures are electrically isolated from one another.

3. The semiconductor device of claim 1 , wherein the silicon carbide drift layer comprises an upper drift layer and a lower drift layer separated by the buried junction structure, wherein the lower drift layer is between the substrate and the upper drift layer, and wherein the upper drift layer has a thickness that is greater than about one micron.

4. The semiconductor device of claim 3 , wherein the buried junction structure has a junction depth, and wherein the semiconductor device has a radius of curvature that is equal to a thickness of the lower drift layer less the first junction depth, wherein the radius of curvature is less than a lateral width of the lower drift layer.

5. The semiconductor device of claim 1 , wherein the first junction depth is greater than about 2 microns.

6. The semiconductor device of claim 1 , wherein the first junction depth is greater than about 4 microns.

7. The semiconductor device of claim 1 , wherein the buried junction structure comprises a plurality of buried regions arranged in a grid.

8. A semiconductor device, comprising:
a silicon carbide substrate having a first conductivity type;
a silicon carbide drift layer having the first conductivity type on the silicon carbide substrate and having an upper surface opposite the silicon carbide substrate; and
a buried junction structure in the silicon carbide drift layer, wherein the buried junction structure comprises a plurality of first regions having a second conductivity type opposite the first conductivity type, wherein the first regions are electrically isolated from one another by a material of the drift layer;
wherein the buried junction structure comprises a first buried junction structure having a first junction depth, and wherein the semiconductor device further comprises a second buried junction structure having a second junction depth that is greater than the first junction depth; and
wherein a distance between the first buried junction structure and the second buried junction structure is about 0.1 micron to 3 microns.

9. The semiconductor device of claim 8 , wherein the silicon carbide drift layer comprises an upper drift layer and a lower drift layer separated by the buried junction structure, wherein the lower drift layer is between the substrate and the upper drift layer, and wherein the upper drift layer has a thickness that is greater than about one micron.

10. The semiconductor device of claim 9 , wherein the semiconductor device has a radius of curvature that is equal to a thickness of the lower drift layer less the second junction depth of the second buried junction structure, wherein the radius of curvature is less than a lateral width of the lower drift layer.

11. The semiconductor device of claim 8 , wherein the first junction depth is greater than about 2 microns.

12. The semiconductor device of claim 8 , wherein the first junction depth is greater than about 4 microns.

Assignees

• Cree Inc

Inventors

• Van Brunt Edward Robert
• Suvorov Alexander V
• Pala Vipindas
• Cheng Lin

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/2042 Primary

  into crystalline silicon carbide · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title