Semiconductor device comprising trench isolation

Patent metadata

Field	Value
Publication number	US-10103067-B1
Application number	US-201715617388-A
Country	US
Kind code	B1
Filing date	Jun 8, 2017
Priority date	Jun 8, 2017
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A method of manufacturing a trench isolation of a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, forming a trench through the semiconductor layer and extending at least partially into the buried oxide layer, forming a liner at sidewalls of the trench, deepening the trench into the semiconductor bulk substrate, filling the deepened trench with a flowable dielectric material, and performing an anneal of the flowable dielectric material.

First claim

What is claimed:

1. A method of manufacturing a trench isolation of a semiconductor device, comprising:
providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on said semiconductor bulk substrate and a semiconductor layer formed on said buried oxide layer;
forming a trench through said semiconductor layer and extending at least partially into said buried oxide layer;
forming a liner at sidewalls of said trench;
deepening said trench into said semiconductor bulk substrate;
filling said deepened trench with a flowable dielectric material;
performing an anneal of said flowable dielectric material;
removing a portion of said annealed flowable dielectric material from an upper portion of said deepened trench; and
filling said upper portion of said deepened trench with an oxide material.

2. The method of claim 1 , further comprising removing said liner after performing said anneal, after removing said portion of said annealed flowable dielectric material, and before filling said upper portion of said deepened trench with said oxide material.

3. The method of claim 1 , wherein said liner is made of a silicon-nitride material or comprises a silicon-nitride material.

4. The method of claim 1 , wherein said semiconductor layer comprises an SiGe region and said liner is formed on a side surface of said SiGe region before said anneal.

5. The method of claim 1 , wherein said semiconductor layer comprises an SiGe region and further comprising forming another trench extending at least partially into said buried oxide layer with a smaller depth than a depth of said deepened trench and forming a liner at sidewalls of said another trench such that a side surface of said SiGe region is covered before said anneal.

6. The method of claim 1 , wherein said liner is formed prior to deepening said trench.

7. The method of claim 1 , further comprising filling said trench with a mask material prior to deepening said trench.

8. A method of manufacturing a trench isolation of a semiconductor device, comprising:
providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on said semiconductor bulk substrate and a semiconductor layer formed on said buried oxide layer;
forming a trench through said semiconductor layer and extending at least partially into said buried oxide layer;
deepening said trench into said semiconductor bulk substrate;
after deepening said trench, forming a liner at sidewalls of said deepened trench;
filling said deepened trench with a flowable dielectric material;
performing an anneal of said flowable dielectric material;
removing a portion of said annealed flowable dielectric material from an upper portion of said deepened trench; and
filling said upper portion of said deepened trench with an oxide material.

9. The method of claim 8 , further comprising removing an upper portion of said liner after performing said anneal, after removing said portion of said annealed flowable dielectric material, and before filling said upper portion of said deepened trench with said oxide material.

10. The method of claim 8 , wherein said liner is made of a nitride material or comprises a nitride material.

11. The method of claim 8 , wherein said semiconductor layer comprises an SiGe region and said liner is formed on a side surface of said SiGe region before said anneal.

12. The method of claim 8 , wherein said semiconductor layer comprises an SiGe region and further comprising forming another trench extending at least partially into said buried oxide layer with a smaller depth than a depth of said deepened trench and forming a liner at sidewalls of said another trench such that a side surface of said SiGe region is covered before said anneal.

13. The method of claim 8 , further comprising filling said trench with a mask material prior to deepening said trench.

14. A method of manufacturing a semiconductor device, comprising:
providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on said semiconductor bulk substrate and a semiconductor layer formed on said buried oxide layer, wherein said semiconductor layer comprises an SiGe region;
forming a first trench through said semiconductor layer and extending at least partially into said buried oxide layer;
forming a second trench spaced apart from said first trench through said semiconductor layer and extending at least partially into said buried oxide layer such that one sidewall of said second trench exposes a side surface of said SiGe region;
forming a first liner at sidewalls of said first trench and a second liner at sidewalls of said second trench;
deepening said first trench into said semiconductor bulk substrate without deepening said second trench;
filling said deepened first trench and said second trench with a flowable dielectric material;
performing an anneal of said flowable dielectric material; and
forming an n-channel transistor and a p-channel transistor separated from each other by said second trench and wherein said SiGe region provides a channel region of said p-channel transistor.

15. The method of claim 14 , further comprising:
removing a portion of said annealed flowable dielectric material from an upper portion of said deepened first trench;
removing said annealed flowable dielectric material from said second trench; and
subsequently filling said upper portion of said deepened first trench and said second trench with an oxide material.

16. The method of claim 15 , further comprising:
removing said first liner after performing said anneal, after removing said portion of said annealed flowable dielectric material from said upper portion of said deepened first trench, and before filling said upper portion of said deepened first trench with said oxide material; and
removing said second liner after performing said anneal, after removing said annealed flowable dielectric material from said second trench, and before filling said second trench with said oxide material.

17. The method of claim 14 , wherein at least one of said first and second liners is made of a nitride material or comprises a nitride material.

18. The method of claim 14 , wherein said first and second liners are formed prior to deepening said first trench.

19. The method of claim 14 , wherein said first and second liners are formed after deepening said first trench.

20. The method of claim 14 , further comprising filling at least said first trench with a mask material prior to deepening said first trench.

Assignees

• Globalfoundries Inc

Inventors

• Baars Peter
• Grasshoff Gunter
• Hueselitz Rico

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6687

  the compound comprising silicon and nitrogen · CPC title

• H10P14/6529

  by exposure to a gas or vapour · CPC title

• H10P14/6522

  introduced into a nitride material, e.g. changing SiN to SiON · CPC title