Process for filling vias in the microelectronics

Patent metadata

Field	Value
Publication number	US-10103029-B2
Application number	US-201615148738-A
Country	US
Kind code	B2
Filing date	May 6, 2016
Priority date	Jan 26, 2011
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.

First claim

What is claimed is:

1. A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, said device comprising a surface having a via feature therein, said via feature comprising a sidewall extending from said surface, and a bottom, said sidewall, said bottom and said surface having a metalizing substrate thereon for deposition of copper, said metalizing substrate comprising a seed layer, the process comprising:
prewetting the metalizing substrate with a pre-wetting solution;
immersing said metalizing substrate in an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 25 micrometers, a depth dimension between 50 micrometers and 300 micrometers, and an aspect ratio greater than about 2:1, said metalizing substrate providing a cathode for electrolytic deposition of copper thereon, the deposition composition comprising:
a source of copper ions;
an acid component selected from among an inorganic acid, an organic sulfonic acid, and mixtures thereof;
an accelerator, wherein the accelerator comprises a water-soluble organic divalent sulfur compound;
a suppressor;
a leveler; and
chloride ions;

establishing an electrodeposition circuit comprising an anode, said electrolytic composition, said cathode, and a power source;
applying a potential between said anode and said cathode that establishes a positive polarity at said anode and a negative polarity at said cathode during a via filling cycle to generate a cathodic electrodeposition current causing reduction of copper ions at said cathode, thereby plating copper onto said substrate at the bottom and sidewall of said via, the via preferentially plating on the bottom and lower sidewall to cause filling of the via from the bottom with copper,
wherein during the filling cycle, bottom up filling of the via stalls due to adsorption of the leveler onto the via, the process further comprises the steps of:
a) reversing polarity of said electrodeposition circuit to generate an anodic current at said metalizing substrate and anodically desorb leveler from the copper plated within the via in one or more anodic current intervals; and
b) resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in said electrodeposition circuit after each of the one or more anodic current intervals;
wherein the one or more anodic current intervals at said metalizing substrate are sufficient in duration and charge transfer density to anodically desorb leveler that has attached to the copper plated within the via; and
wherein the application of the one or more anodic current intervals restores bottom up plating, thereby reducing time required for metallizing the through silicon via feature.

2. A process as set forth in claim 1 , wherein a maximum cumulative extent of anodic charge transfer at said metalizing substrate in a sum of all said anodic current intervals is not greater than an average of about 1.8 coulombs/cm 2 integrated over a total electrodic surface area of said metalizing substrate.

3. A process as set forth in claim 1 , wherein a cumulative duration of all anodic current intervals at said metalizing substrate during said filling cycle is not more than 50 seconds.

4. A process as set forth in claim 1 , wherein at least one of said anodic current intervals prevails for a period of at least 0.1 seconds.

5. A process as set forth in claim 4 wherein at least one of said anodic current intervals prevails for a period of at least 0.5 seconds.

6. A process as set forth in claim 1 , wherein at least one of said anodic current intervals prevails for a period between about 0.1 and about 100 seconds.

7. A process as set forth in claim 1 , in which each of at least two of said anodic current intervals prevail for a period of at least 0.1 second.

8. A process as set forth in claim 1 , wherein at least one of said anodic current intervals prevails to an extent of an average charge transfer of at least about 5×10 −5 coulombs/cm 2 integrated over a total electrodic area of said metalizing substrate.

9. A process as set forth in claim 1 wherein said filling cycle comprises a plurality of anodic current intervals of material duration, each such anodic intervals of material duration extending for a period of at least 0.6 seconds, the period of cathodic current at said metalizing substrate between successive anodic current intervals of material duration being at least about 0.5 minutes.

10. A process as set forth in claim 1 wherein said filling cycle comprises a plurality of faradaically material anodic current intervals at said metalizing substrate in each of which an average anodic charge transfer is at least about 5×10 −5 coulombs/cm 2 integrated over a total electrodic area of said metalizing substrate, and wherein, between successive faradaically material anodic current intervals, an integrated average cathodic current charge transfer over a total surface area of said cathode is at least about 1.5×10 −2 coulombs/cm 2 .

11. A process as set forth in claim 9 wherein, during each said anodic current interval of material duration, a current density across an electrode surface of the metalizing substrate is maintained at an average of between about 0.1 and about 100 mA/cm 2 integrated over the total electrodic area of said metalizing substrate.

12. A process as set forth in claim 11 wherein, during each said anodic current interval of material duration and during each said faradaically material anodic current interval, the current density across the electrode surface of the metalizing substrate is maintained at an average of between about 0.1 and about 100 mA/cm 2 integrated over a total electrodic area of said metalizing substrate.

13. A process as set forth in claim 1 wherein the via is at least 90% filled after a filling cycle of no greater than 90 minutes.

14. A process as set forth in claim 1 wherein the copper filling in the via is at least one of substantially free of seams and voids or substantially free of mounds and protrusions.

15. A process as set forth in claim 1 wherein each of one or more anodic current intervals is effective to desorb leveler from an electrodic surface, wherein an average current density integrated over the surface of the metalizing substrate is increased upon resumption of cathodic current relative to a current density prior to said anodic current interval.

16. A process as set forth in claim 15 wherein said anodic current intervals are effective to desorb suppressor from the copper surface within the via.

17. A process as set forth in claim 1 , wherein a ratio of the cumulative duration of cathodic current during copper deposition within said filling cycle to the cumulative duration of all anodic current intervals at said metalizing substrate is at least about 80:1.

18. The process according to claim 1 , wherein the leveler comprises a derivative of a vinyl pyridine.

19. The process according to claim 18 , wherein the leveler is a homopolymer of vinyl pyridine, a copolymer of vinyl pyridine, a quaternized salt of vinyl pyridine, a quaternized salt of a homopolymer of vinyl pyridine or a quaternized salt of a copolymer of vinyl pyridine.

20. The process according to claim 1 , wherein a ratio of cumulative charge transfer in said circuit during copper deposition within said filling cycle to the cumulative charge transfer during the one or more anodic current intervals at said metalizing substrate is at

Assignees

• Macdermid Enthone Inc

Inventors

• Richardson Thomas B
• Abys Joseph A
• Shao Wenbo
• Wang Chen
• Paneccasio Vincent
• Wang Cai
• Lin Sean Xuan
• Antonellis Theodore

Classifications

• H10W20/0261

  characterised by the filling method or the material of the conductive fill · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/043

  for electroplating · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title