Method and apparatus for adaptive graphics compression and display buffer switching

Patent metadata

Field	Value
Publication number	US-10102828-B2
Application number	US-201314655183-A
Country	US
Kind code	B2
Filing date	Jan 9, 2013
Priority date	Jan 9, 2013
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

There is provided a multimedia computing apparatus for processing and displaying video data with overlay graphic data, said multimedia computing apparatus comprising a compression unit arranged to compress graphic overlay data prior to storage of said compressed overlay graphic data in a compressed display buffer, and a control unit arranged to determine when to compress the overlay graphic data dependent upon a refresh parameter of the overlay graphic data. There is also provided a method of adaptively compressing graphics data in a multimedia computing system comprising dynamically controlling compression of graphic overlay data in a display buffer dependent upon a refresh parameter of the graphic overlay data.

First claim

The invention claimed is:

1. A System on Chip (SoC) integrated circuit multimedia computing apparatus for processing and displaying video data with graphic overlay data, said multimedia computing apparatus comprising:
a main processor, a CPU and a GPU, the main processor comprising a graphics frame buffer, an overlay circuit, a compression circuit and a control circuit:
the graphics frame buffer to store the graphic overlay data of a plurality of pixels to be displayed;
the overlay circuit to combine the video data with the graphic overlay data to produce a display data;
the compression circuit to compress the graphic overlay data prior to storage of said compressed graphic overlay data;
the control circuit including a first terminal coupled to a terminal of the compression circuit,
the control circuit to determine when to compress the graphic overlay data dependent upon a refresh parameter of the graphic overlay data,
wherein the graphic overlay data is compressed only while the graphic overlay data is stable, and
wherein the graphic overlay data comprises shared data received from the main processor, the CPU and the GPU;
a shared on-die compressed display buffer arranged to store at least a first portion of the compressed graphic overlay data from the compression circuit; and
an external shared memory including a shared compressed display buffer to store a second portion of the compressed graphic overlay data when the shared on-die compressed display buffer is full,
wherein a portion of the external shared memory not used to store the second portion of the compressed graphic overlay data is powered down.

2. The multimedia computing apparatus of claim 1 , further comprising a decompression circuit including a terminal coupled to a second terminal of the control circuit, the decompression circuit to decompress the graphic overlay data from the display buffer prior to supply of the graphic overlay data to the overlay circuit.

3. The multimedia computing apparatus of claim 1 , wherein the shared on-die compressed display buffer is a dedicated on-die display buffer, or a dedicated portion of a shared cache on the SoC.

4. The multimedia computing apparatus of claim 1 , further comprising at least one direct memory access (DMA) circuit arranged to load uncompressed graphic overlay data from an uncompressed display buffer in the external shared memory prior to the uncompressed graphic overlay data being combined as the graphic overlay data with the video data.

5. The multimedia computing apparatus of claim 1 , wherein the external memory is dual data rate (DDR) memory.

6. The multimedia computing apparatus of claim 1 , wherein the refresh parameter of the graphic overlay data is dependent upon system or user interaction timing with the graphic data.

7. The multimedia computing apparatus of claim 6 , wherein user interaction timing is dependent on a length of time since a last user interaction with the multimedia computing apparatus.

8. The multimedia computing apparatus of claim 1 , wherein the graphic overlay data is rendered from information with a low rate of change over time.

9. A method of adaptively compressing graphic overlay data in a System on Chip (SoC) integrated circuit multimedia computing system, said multimedia computing system comprising a main processor, a CPU and a GPU,
the method comprising:
storing graphic overlay data of a plurality of pixels to be displayed;
dynamically controlling compression of the graphic overlay data in a display buffer dependent upon a refresh parameter of the graphic overlay data,
wherein the graphic overlay data is compressed only while the graphic overlay data is stable, and wherein the graphic overlay data comprises shared data received from the main processor, the CPU and the GPU;
storing compressed graphic overlay data in a shared on-die compressed display buffer located within the same semiconductor die as a compression circuit;
storing a portion of the compressed graphic overlay data in a shared compressed display buffer of an external shared memory when the shared on-die compressed display buffer is full;
powering down a portion of the external shared memory not used to store the portion of the compressed graphic overlay data; and
combining, via an overlay circuit, video data with the graphic overlay data to produce a display data.

10. The method of claim 9 , further comprising decompressing the compressed graphic overlay data from the shared display buffer prior to supply of the graphic overlay data to the overlay circuit.

11. The method of claim 9 , further comprising loading uncompressed graphic overlay data from an uncompressed graphic display buffer located in external shared memory prior to the uncompressed graphic overlay data being combined as the graphic overlay data with the video data.

12. The method of claim 9 , wherein the refresh parameter of the graphic overlay data is dependent upon user interaction timing with the graphic data, or on a length of time since a last user interaction with the multimedia computing system.

13. A System on Chip (SoC) integrated circuit computing apparatus comprising:
a main processor, a CPU and a GPU,
the main processor comprising a graphics frame buffer to store graphic overlay data of a plurality of pixels to be displayed;
an overlay circuit to combine video data with the graphic overlay data to produce a display data;
a compression circuit including a terminal to receive an enable signal, the compression circuit to dynamically control compression of the graphic overlay data in a display buffer dependent upon a refresh parameter of the graphic overlay data and based on the enable signal,
wherein the graphic overlay data is compressed only while the graphic overlay data is stable and
wherein the graphic overlay data comprises shared data received from the main processor, the CPU and the GPU;
a shared on-die compressed display buffer arranged to store at least a first portion of the compressed graphic overlay data from the compression circuit; and
an external shared memory including a shared compressed display buffer to store a second portion of the compressed graphic overlay data when the shared on-die compressed display buffer is full,
wherein a portion of the external shared memory not used to store the second portion of the compressed graphic overlay data is powered down.

14. The computing apparatus of claim 13 , wherein the on-die compressed display buffer is a dedicated on-die display buffer, or a dedicated portion of a shared cache on the SoC.

15. The computing apparatus of claim 13 , further comprising at least one direct memory access DMA circuit arranged to load uncompressed graphic overlay data from an uncompressed display buffer in external shared memory prior to the uncompressed graphic overlay data being combined as the graphic overlay data with the video data.

16. The computing apparatus of claim 13 , further comprising: a control circuit including a terminal coupled to a terminal of the compression circuit, the control circuit to determine when to store the graphic overlay data in an on-die display buffer or an off-die display buffer based on the refresh parameter of the graphic overlay data.

Assignees

• Priel Michael
• Ferderber Ran
• Zarubinsky Michael
• Nxp Usa Inc

Inventors

• Priel Michael
• Ferderber Ran
• Zarubinsky Michael

Classifications

• G09G5/36

  characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory · CPC title

• G09G2340/125

  wherein one of the images is motion video · CPC title

• G09G5/377 Primary

  for mixing or overlaying two or more graphic patterns (G09G5/02, G09G5/397 take precedence) · CPC title

• G09G5/397 Primary

  Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay (G09G5/02 takes precedence) · CPC title

• G09G2360/18

  Use of a frame buffer in a display terminal, inclusive of the display panel · CPC title