Array substrate and display device including the same

Patent metadata

Field	Value
Publication number	US-10102813-B2
Application number	US-201615394120-A
Country	US
Kind code	B2
Filing date	Dec 29, 2016
Priority date	Dec 31, 2015
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

An array substrate of a display device includes an active area with curved corner portions and a compensation unit to reduce a difference in a parasitic capacitance of each gate line and each data line. Also, a plurality of data lines disposed to overlap the corner portions of the active area may be disposed with a different width therebetween to reduce a difference in parasitic capacitance of each gate line or data line disposed to overlap the corner portions of the active area and to reduce a resistance difference between data lines. Therefore, a degree of delay of a signal transferred through a plurality of gate lines or data lines can be similar in each gate line or data line, so that a defect can be prevented in a displayed image.

First claim

What is claimed is:

1. An array substrate having an active area and a non-active area, comprising:
first, second, and third areas and a plurality of pixels disposed in the active area, the first area with curved corner portions, the second area adjacent to the first area, and the third area adjacent to the first area and spaced apart from the second area, the pixels disposed where a plurality of gate lines and a plurality of data lines intersect each other;
a first gate driving circuit unit disposed in the non-active area and having a first circuit block group configured to sequentially supply a scan signal to the gate lines and having a curve shape corresponding to the first area and a second circuit block group disposed corresponding to the second area;
first and second link line groups disposed in the non-active area the first link line group connected to the data lines and corresponding to the first area, and the second link line group disposed corresponding to the third area; and
a first compensation unit having a compensation electrode receiving a common voltage from a power supply unit through a curved common voltage line connected to a common voltage terminal, disposed outside the active area and disposed at intersections between a plurality of gate lines extended from the first circuit block group and a plurality of data lines extended from the first link line group to supply a first parasitic capacitance to the plurality of gate lines extended from the first circuit block group and the plurality of data lines extended from the first link line group, and reducing a difference in parasitic capacitance of each gate line or each data line.

2. The array substrate according to claim 1 , wherein the first compensation unit has a curve shape corresponding to the first area.

3. The array substrate according to claim 1 , wherein the compensation electrode is formed of the same material and the same shape as the common electrode disposed on each of the pixels.

4. The array substrate according to claim 1 , further comprising fourth and fifth areas, the fourth area adjacent to the third area and having a curved corner portion and the fifth area adjacent to the fourth area and spaced apart from the third area.

5. The array substrate according to claim 4 , further comprising a third link line group disposed corresponding to the fourth area and a fourth link line group disposed corresponding to the third area.

6. The array substrate according to claim 4 , further comprising second gate driving circuit unit disposed in the non-active area and having a third circuit block group configured to sequentially supply the scan signal to the gate lines and disposed in a curve shape corresponding to the fourth area and a fourth circuit block group disposed corresponding to the fifth area.

7. The array substrate according to claim 6 , further comprising a second compensation unit disposed in the non-active area and disposed at intersections between the gate lines extended from the third circuit block group and the data lines extended from the third link line group to supply a second parasitic capacitance to the gate lines extended from the third circuit block group and the data lines extended from the third link line group.

8. The array substrate according to claim 1 , wherein the plurality of data lines extended from the first link line group has a resistance equal to that of a plurality of data lines extended from the second link line group.

9. The array substrate according to claim 1 , wherein the plurality of data lines extended from the first link line group has a width greater than that of a plurality of data lines extended from the second link line group.

10. The array substrate according to claim 1 , wherein the active area has curve shape corners.

11. A display device comprising:
a first gate driving circuit unit disposed in a non-active area, and having first and second circuit block groups, the first circuit block group configured to sequentially supply a scan signal to a plurality of gate lines in an active area having a curve shape;
first, second, third link line groups disposed in the non-active area;
a data driving circuit unit configured to supply a data voltage to the first and second data link line groups;
a timing controller configured to supply control signals to the first gate driving circuit unit and the data driving circuit unit;
a power supply unit configured to supply a common voltage to a common voltage terminal; and
a first compensation unit having a compensation electrode receiving the common voltage from the power supply unit through a curved common voltage line connected to the common voltage terminal, disposed outside the active area and disposed at intersections between the plurality of gate lines extended from the first circuit block group and a plurality of data lines extended from the first link line group to supply a first parasitic capacitance to the plurality of gate lines extended from the first circuit block group and the plurality of data lines extended from the first link line group, and compensating for a parasitic capacitance between the gate lines and the data lines and a resistance of the data lines at curve shape corners of the active area.

12. The display device according to claim 11 , further comprising a second gate driving circuit unit disposed in the non-active area and having third and fourth circuit block groups, the third circuit block group configured to sequentially supply the scan signal to the gate lines and having a curve shape.

13. The display device according to claim 12 , further comprising a second compensation unit disposed in the non-active area and disposed at intersections between a plurality of the gate lines extended from the third circuit block group and a plurality of data lines extended from the third link line group to supply a second parasitic capacitance to the plurality of gate lines extended from the third circuit block group and the plurality of data lines extended from the third link line group, to compensate for the parasitic capacitance between the gate lines and the data lines and the resistance of the data lines at the curve shape corners of the active area.

14. The display device according to claim 11 , wherein the plurality of data lines extended from the first link line group has a resistance equal to that of a plurality of data lines extended from the second link line group.

15. The display device according to claim 11 , wherein the plurality of data lines extended from the first link line group has a width greater than that of a plurality of data lines extended from the second link line group.

16. An array substrate for display device, having an active area and a non-active area, comprising:
a first gate driving circuit unit disposed in the non-active area, and having first and second circuit block groups, the first circuit block group configured to sequentially supply a scan signal to a plurality of gate lines in an active area having a curve shape; and
a first compensation unit having a compensation electrode receiving a common voltage from a power supply unit through a curved common voltage line connected to a common voltage terminal, disposed outside the active area and disposed where a plurality of gate lines extended from the first circuit block group and a plurality of data lines extended from a first link line group intersect each other, the first compensation unit to supply a first parasitic capacitance to the plurality of gate lines extended from the first circuit block group and the plurality of data lines extended from th

Assignees

• Lg Display Co Ltd

Inventors

• Heo Seounguk
• Jun Sahnglk
• Yoon Kyeusang

Classifications

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• H01L51/52

  Electricity · mapped topic

• H01L27/3276

  Electricity · mapped topic

• G09G3/3611 Primary

  Control of matrices with row and column drivers · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title