Hardware enforced content protection for graphics processing units

Patent metadata

Field	Value
Publication number	US-10102391-B2
Application number	US-201514821174-A
Country	US
Kind code	B2
Filing date	Aug 7, 2015
Priority date	Aug 7, 2015
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

This disclosure proposes techniques for graphics processing. In one example, a graphics processing unit (GPU) is configured to access a memory according to one of an unsecure mode and a secure mode. The GPU may include a memory access controller configured to direct memory transactions from at least one hardware unit of the GPU to an unsecure memory unit or a secure memory unit based on the unsecure mode or secure mode and a resource descriptor associated with a memory resource.

First claim

What is claimed is:

1. An apparatus for graphics processing comprising:
a graphics processing unit (GPU) configured to access a first memory unit according to one of an unsecure mode and a secure mode and a respective resource descriptor associated with each of a plurality of memory resources, wherein each respective resource descriptor includes tag information indicating how each respective memory resource of the plurality of memory resources is to be used, and wherein each respective resource descriptor is a secure resource descriptor or an unsecure resource descriptor, each secure resource descriptor allowing reads and writes to associated memory resources of the plurality of memory resources in the secure mode, each unsecure resource descriptor allowing reads from associated resources of the plurality of memory resources in the secure mode, and each unsecure resource descriptor disallowing writes to associated resources of the plurality of memory resources in the secure mode, the GPU comprising:
a memory access controller configured to read the respective resource descriptor associated with each of the plurality of memory resources,
the memory access controller configured to receive a request for a memory transaction to the first memory unit,
the memory access controller configured to, in response to the request, direct all read and write memory transactions relating to memory resources of the plurality of memory resources for which the respective resource descriptor is the secure resource descriptor to a secure portion of the first memory unit when the GPU is operating according to the secure mode,
the memory access controller configured to, in response to the request, direct all read memory transactions relating to memory resources of the plurality of memory resources for which the respective resource descriptor is the unsecure resource descriptor to an unsecure portion of the first memory unit when the GPU is operating according to the secure mode, and
the memory access controller configured to, in response to the request, drop all write memory transactions relating to memory resources of the plurality of memory resources for which the respective resource descriptor is the unsecure resource descriptor when the GPU is operating according to the secure mode; and
a front end command processor configured to write data to the unsecure portion of the first memory regardless of whether the GPU is in the unsecure mode or the secure mode, wherein the front end command processor does not have read access to the secure portion of the first memory unit.

2. The apparatus of claim 1 , wherein the memory access controller is further configured to, in response to the request, direct read and write memory transactions relating to memory resources of the plurality of memory resources for which the respective resource descriptor is the unsecure resource descriptor to an unsecure portion of the first memory unit when the GPU is operating according to the unsecure mode, and
the memory access controller is further configured to, in response to the request, drop read and write memory transactions relating to memory resources of the plurality of memory resources for which the respective resource descriptor is the secure resource descriptor when the GPU is operating according to the unsecure mode.

3. The apparatus of claim 1 , wherein the memory access controller is configured to write data to the secure portion of the first memory unit utilizing a secure memory management unit, the secure memory management unit utilizing a secure page table containing address ranges for the secure portion of the first memory unit, and wherein the memory access controller is configured to read data from the unsecure portion of the first memory unit utilizing an unsecure memory management unit, the unsecure memory management unit utilizing an unsecure page table containing address ranges for the unsecure portion of the first memory unit.

4. The apparatus of claim 3 , wherein the memory access controller reads and writes data according to a virtual memory address from a range of virtual memory addresses, wherein the range of virtual memory addresses includes a first range of virtual memory addresses relating to entries in the secure page table utilized by the secure memory management unit, and a second range of virtual memory addresses relating to entries in the unsecure page table utilized by the unsecure memory management unit.

5. The apparatus of claim 4 , further comprising:
a second memory unit storing a graphics driver, the graphics driver configured to place the GPU in the secure mode or the unsecure mode.

6. The apparatus of claim 5 , further comprising:
the secure memory management unit;
the unsecure memory management unit; and
a central processing unit (CPU) executing a secure operating system and the graphics driver, the secure operating system configured to supply the secure page table to the secure memory management unit and the unsecure page table to the unsecure memory management unit.

7. The apparatus of claim 6 , wherein the GPU further comprises a clear register and one or more internal memories, and wherein the secure operating system is configured to send an instruction to the clear register that causes the GPU to clear and invalidate at least some content from the one or more internal memories when the GPU is transitioned from the secure mode to the unsecure mode.

8. The apparatus of claim 6 , wherein the GPU further comprises a command stream register and one or more internal memories, and wherein the graphics driver is configured to send an instruction to the command stream register that causes the GPU to clear and invalidate at least some content from the one or more internal memories when the GPU is transitioned from the secure mode to the unsecure mode.

9. A method comprising:
reading a respective resource descriptor for a respective memory resource of a plurality of memory resources, wherein each respective resource descriptor includes tag information indicating how each respective memory resource of the plurality of memory resources is to be used, and wherein each respective resource descriptor is a secure resource descriptor or an unsecure resource descriptor, each secure resource descriptor allowing reads and writes to associated memory resources of the plurality of memory resources in a secure mode, each unsecure resource descriptor allowing reads from associated resources of the plurality of memory resources in the secure mode, and each unsecure resource descriptor disallowing writes to associated resources of the plurality of memory resources in the secure mode;
receiving a request for a memory transaction to a first memory unit;
directing, in response to the request, read and write memory transactions relating to memory resources of the plurality of memory resources for which the respective resource descriptor is the secure resource descriptor to a secure portion of the first memory unit when a graphics processing unit (GPU) is operating according to the secure mode;
directing, in response to the request, read memory transactions relating to memory resources of the plurality of memory resources for which the respective resource descriptor is the unsecure resource descriptor to an unsecure portion of the first memory unit when the GPU is operating according to the secure mode;
dropping, in response to the request, write memory transactions relating to memory resources of the plurality of memory resources for which the respective resource descriptor is the unsecure resource descriptor when the GPU is operating according to the secure mode; and
writing data, by a front end command processor configured, to the unsecure portion of the firs

Assignees

• Qualcomm Inc

Inventors

• Sharp Colin Christopher
• Viswanathan Ramesh

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F21/6218 Primary

  to a system of files or objects, e.g. local or distributed file system or database · CPC title

• G06T1/60

  Memory management · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title