Dynamically-adjusted host memory buffer

Patent metadata

Field	Value
Publication number	US-10102135-B2
Application number	US-201615092100-A
Country	US
Kind code	B2
Filing date	Apr 6, 2016
Priority date	Apr 6, 2016
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

Host memory buffer is dynamically adjusted based on performance. As memory pages are accessed, one or more counts of the memory pages are maintained. If the counts indicate some of the memory pages are identical, then a portion of host system memory allocated to buffer cache may be reduced or decremented in response to repetitive access. However, if the counts indicate different memory pages are accessed, then the host system memory allocated to the buffer cache may be increased or incremented.

First claim

What is claimed is:

1. A method for optimizing a buffer cache in a system memory of a host system, comprising:
determining, by a disk controller, a capacity associated with a solid state memory drive, the solid state memory drive accessible to the disk controller as a peripheral device via an interface;
determining, by the disk controller, the system memory available from the host system;
determining, by the disk controller, a count of memory pages in the system memory accessed via the solid state memory drive; and
dynamically allocating, by the disk controller, a portion of the system memory as the buffer cache based on a performance threshold associated with the solid state memory drive, the buffer cache storing a flash translation layer file associated with the solid state memory drive, the buffer cache dynamically allocated based on the count of the memory pages accessed via the solid state memory drive by comparing the count of the memory pages to the performance threshold;
wherein if the count of the memory pages equals or exceeds the performance threshold, then increasing a size of the buffer cache; and
wherein if the count of the memory pages is less than the performance threshold, then decreasing the size of the buffer cache.

2. The method of claim 1 , further comprising configuring an initial value of the size of the buffer cache based on the capacity associated with the solid state memory drive.

3. The method of claim 1 , further comprising configuring an initial value of the size of the buffer cache based on the system memory available from the host system.

4. The method of claim 1 , further comprising determining the count of different ones of the memory pages accessed via the solid state memory drive.

5. The method of claim 1 , further comprising determining the count of repetitive ones of the memory pages accessed via the solid state memory drive.

6. An information handling system, comprising:
a processor; and
a memory device accessible to the processor, the memory device storing instructions that when executed cause the processor to perform operations including:
determining a capacity associated with a solid state memory drive, the solid state memory drive accessible to the processor as a peripheral device via an interface;
determining a count of memory pages in a system memory accessed via the solid state memory drive;
dynamically allocating a portion of the memory device as a buffer cache based on a performance threshold associated with the solid state memory drive, the buffer cache storing a flash translation layer file associated with the solid state memory drive, the buffer cache dynamically allocated based on the count of the memory pages accessed via the solid state memory drive;
comparing the count of the memory pages to the performance threshold;
increasing a size of the buffer cache in response to the count of the memory pages equaling or exceeding the performance threshold; and
decreasing the size of the buffer cache in response to the count of the memory pages less than the performance threshold.

7. The system of claim 6 , wherein the operations further comprise configuring an initial value of the size of the buffer cache based on the capacity associated with the solid state memory drive.

8. The system of claim 6 , wherein the operations further comprise configuring an initial value of the size of the buffer cache based on a system memory.

9. The system of claim 6 , wherein the operations further comprise determining the count of different ones of the memory pages accessed via the solid state memory drive.

10. The system of claim 6 , wherein the operations further comprise determining the count of repetitive ones of the memory pages accessed via the solid state memory drive.

11. A memory device storing instructions that when executed cause a processor to perform operations, the operations comprising:
determining a capacity associated with a solid state memory drive, the solid state memory drive accessible to the processor as a peripheral device via an interface;
determining a count of memory pages in a system memory accessed via the solid state memory drive;
dynamically allocating a portion of the memory device as a buffer cache based on a performance threshold associated with the solid state memory drive, the buffer cache storing a flash translation layer file associated with the solid state memory drive, the buffer cache dynamically allocated based on the count of the memory pages accessed via the solid state memory drive;
comparing the count of the memory pages to the performance threshold;
increasing a size of the buffer cache in response to the count of the memory pages equaling or exceeding the performance threshold; and
decreasing the size of the buffer cache in response to the count of the memory pages less than the performance threshold.

12. The memory device of claim 11 , wherein the operations further comprise configuring an initial value of the size of the buffer cache based on the capacity associated with the solid state memory drive.

13. The memory device of claim 11 , wherein the operations further comprise configuring an initial value of the size of the buffer cache based on a system memory.

14. The memory device of claim 11 , wherein the operations further comprise determining the count of different ones of the memory pages accessed via the solid state memory drive.

Assignees

• Dell Products Lp

Inventors

• Zaretsky Lee B
• Knepper Lawrence E

Classifications

• G06F2212/281

  Single cache · CPC title

• G06F2212/222

  Non-volatile memory · CPC title

• G06F12/0871 Primary

  Allocation or management of cache space · CPC title

• G06F2212/6046

  Using a specific cache allocation policy other than replacement policy · CPC title

• G06F2212/313

  In storage device · CPC title