System and method for generating cross-core breakpoints in a multi-core microcontroller

Patent metadata

Field	Value
Publication number	US-10102050-B2
Application number	US-201615012287-A
Country	US
Kind code	B2
Filing date	Feb 1, 2016
Priority date	Feb 5, 2015
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

In a debugging method for an integrated circuit device which has multiple processing cores, a debugging breakpoint is activated at a first processor core in the integrated circuit device. Upon activation, the debugging breakpoint stops execution of instructions in the first processor core and the debugging breakpoint is communicated to a second processor core in the integrated circuit device.

First claim

What is claimed is:

1. An integrated circuit device comprising a plurality of microcontrollers operating independently from each other, the integrated circuit further comprising:
a first microcontroller of said plurality of microcontrollers comprising a first processor core, associated first program memory and first emulator logic for activating a first processor core breakpoint, the first microcontroller further comprising a plurality of first peripheral devices, wherein one of the first peripheral devices is a serial communication peripheral;
a breakpoint register within the first microcontroller and coupled with said first processor core for configuring a debugging breakpoint in the first processor core comprising at least one bit for enabling a cross breakpoint;
a second microcontroller of said plurality of microcontrollers comprising a second processor core communicatively coupled to the first processor core and including second emulator logic, wherein the second microcontroller comprises second program memory associated with the second processor core and a plurality of second peripheral devices, wherein one of the second peripheral devices is a serial communication peripheral; and
a first cross breakpoint logic within the first emulator logic which, when said at least one bit is set, is configured to communicate a cross breakpoint signal by the first emulator logic at the first processor core to the second processor core thereby stopping execution of instructions in the second processor core.

2. A system comprising an integrated circuit device according to claim 1 , further comprising:
a host computer coupled with an in-circuit emulator or debugger, wherein the in-circuit emulator or debugger is coupled with the first emulator logic of the first microcontroller and wherein the second microcontroller is coupled with the host computer through said second serial communication peripheral.

3. A system comprising an integrated circuit device according to claim 1 , further comprising:
a host computer coupled with a first and second in-circuit emulator or debugger, wherein the first in-circuit emulator or debugger is coupled with the first emulator logic of the first microcontroller and wherein the second in-circuit emulator or debugger is coupled with the second emulator logic of the second microcontroller.

4. An integrated circuit device in accordance with claim 1 , wherein the second emulator logic comprises a second cross breakpoint logic configured to communicate a breakpoint activated by the second emulator logic at the second processor core to the first processor core.

5. An integrated circuit device in accordance with claim 1 , wherein the first cross breakpoint logic communicates the breakpoint as an interrupt request to an interrupt input associated with the second processor core.

6. An integrated circuit device in accordance with claim 5 , wherein the break point register comprises one or more cross breakpoint interrupt enable bits operable to enable the first cross breakpoint logic to communicate the interrupt request to the interrupt input associated with the second processor core.

7. An integrated circuit device in accordance with claim 1 , wherein each emulator logic comprises an interface coupled with a set of external pins.

8. An integrated circuit device in accordance with claim 7 , wherein a first set of peripheral devices is integrated within the integrated circuit devices and coupled with the first processor core thereby forming a first microcontroller and a second set of peripheral devices is integrated within the integrated circuit device and coupled with the second processor core thereby forming a second microcontroller.

9. An integrated circuit device in accordance with claim 7 , wherein the first microcontroller is operating as a master and the second microcontroller is operating as a slave.

10. An integrated circuit device in accordance with claim 8 , wherein the first set of peripheral devices and/or the second set of peripheral devices comprises a serial communication peripheral.

11. An integrated circuit device in accordance with claim 1 , wherein the first processor core is clocked by a first system clock and the second processor core is clocked by a second system clock which is different than the first system clock.

12. An integrated circuit device in accordance with claim 11 , further comprising clock crossing circuitry interfacing the first cross breakpoint logic with the second processor core.

13. An integrated circuit device in accordance with claim 12 , wherein the clock crossing circuitry is coupled between the first cross breakpoint logic and an interrupt controller associated with the second processor core.

14. An integrated circuit device in accordance with claim 1 , wherein the first and/or second emulator logic is operable to configure a plurality of programmable breakpoints.

15. An integrated circuit device in accordance with claim 14 , wherein said programmable breakpoints comprise instruction breakpoints and data breakpoints.

Assignees

• Microchip Tech Inc

Inventors

• Kris Bryan
• Catherwood Mike
• Mickey Dave
• Fall Brian
• Wilkie Calum
• Sheard Vincent
• Dumais Alex

Classifications

• G06F11/2231

  to test interrupt circuits · CPC title

• G06F11/0772 Primary

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/3652

  in-circuit-emulation [ICE] arrangements · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/2851

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title