Linear regulator with real-time frequency compensation function

Patent metadata

Field	Value
Publication number	US-10101758-B2
Application number	US-201715834903-A
Country	US
Kind code	B2
Filing date	Dec 7, 2017
Priority date	Dec 13, 2016
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

The present invention relates to a linear regulator with real-time frequency compensation function, which belongs to the technical field of analog integrated circuits. The part of frequency compensation of the present invention includes the dual-frequency compensation networks and compensation transfer switcher, and the pulse delay circuit. The dual-frequency compensation networks and compensation transfer switcher provide the corresponding frequency compensation for linear regulator under two different capacitive loads. The pulse delay circuit generates a set of signals which have a delay related to the switch-pulse signals to control the access of the compensation transfer switcher and capacitive load. The advantages of the present invention are that the circuit structure is simple, without complex feedback control circuits, the excessive power dissipation is extremely low, and it is applied to such special use of linear regulator with switched capacitive load that it can option the loop frequency compensation in real-time to ensure the linear regulator has the optimal stability and load transient response.

First claim

What is claimed is:

1. A linear regulator with real-time frequency compensation function, the linear regulator comprising:
an error amplifier EA,
a regulate transistor M P ,
a capacitive load C G controlled by switching pulse signalsφ 1 ,
dual-frequency compensation networks,
a compensation transfer switcher, and
a pulse delay circuit,
the non-inverting input of the error amplifier EA connects to the output of the linear regulator V o , and the inverting input of the error amplifier EA connects to a reference voltage V REF , the output of the error amplifier EA connects to the gate of the regulate transistor M P ,
the source of the regulate transistor M P connects to a power source, and the drain of the regulate transistor M P connects to the output of the linear regulator V o ,
the capacitive load C G controlled by the switching pulse signals is connected between the ground and the drain of the regulate transistor M P ,
one port of the dual-frequency compensation networks and compensation transfer switcher connects to the output of the error amplifier EA and the gate of the regulate transistor M P , and another port of the dual-frequency compensation networks connects to the output of the linear regulator or connects to ground, a control port of the dual-frequency compensation networks and compensation transfer switcher connects to the switching pulse signals φ 1 ,
an input port P i of the pulse delay circuit connects to the switching pulse signals φ 1 , and an output port P o of the pulse delay circuit connects to a control switcher of the capacitive load C G .

2. The linear regulator according to claim 1 , wherein the dual-frequency compensation networks and compensation transfer switcher includes a first compensation network, a second compensation network, and a compensation transfer switcher, wherein the compensation transfer switcher is used for controlling and real-time switching the connection ways of the first compensation network and the second compensation network which includes at least one of connecting one of the two compensation networks, connecting both of the two compensation networks in parallel, and connecting both of the two compensation networks in series.

3. The linear regulator according to claim 2 wherein the first compensation network and the second compensation network are used for providing the corresponding frequency compensation for the linear regulator under two different capacitive loads.

4. The linear regulator according to claim 1 wherein the pulse delay circuit provides a fixed-delay time to make the dual-frequency compensation networks switch earlier than connecting to a switch of the capacitive load of the linear regulator.

Assignees

• Univ Electronic Sci & Tech China

Inventors

• Luo Ping
• Qiu Shuangjie
• Wang Kangle
• Liu Zelang
• Huang Long

Classifications

• G05F1/462

  as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic · CPC title

• H03K17/04163

  in field-effect transistor switches · CPC title

• G05F1/461

  using an operational amplifier as final control device · CPC title

• H03K17/56

  by the use, as active elements, of semiconductor devices (using diodes H03K17/74) · CPC title

• G05F1/563

  including two stages of regulation at least one of which is output level responsive, e.g. coarse and fine regulation · CPC title