Array substrate, display panel, display device, and method for fabricating array substrate

Patent metadata

Field	Value
Publication number	US-10101626-B2
Application number	US-201615324053-A
Country	US
Kind code	B2
Filing date	Jan 29, 2016
Priority date	Sep 16, 2015
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

An array substrate, a display panel, a display device, and a method for fabricating an array substrate are provided. The array substrate comprises gate lines and data lines on a substrate plate which are insulated from each other and intersect to define sub-pixel units, and the data lines comprise a first data line and a second data line which are arranged side by side between two neighboring columns of sub-pixel units. Between two of the sub-pixel units which are neighbors in a column direction, at least a portion of the first data line is arranged in a layer different from the neighboring second data line. At least a part of the first data line is arranged in a layer different from that of the neighboring second data line, to overcome the problem of short circuit between dual data lines.

First claim

What is claimed is:

1. An array substrate, comprising gate lines and data lines on a substrate plate which are insulated from each other and intersect to define sub-pixel units, wherein a thin film transistor and a pixel electrode are formed in each of the sub-pixel units, the data lines comprise a first data line and a second data line which are arranged side by side between two neighboring columns of sub-pixel units, wherein in every two neighboring columns of sub-pixel units, sub-pixel units in odd rows are connected with the first data line, and sub-pixel units in even rows are connected with the second data line, wherein between two of the sub-pixel units which are neighbors in a column direction, at least a portion of the first data line is arranged in a layer different from the neighboring second data line,
wherein the first data line comprises first segments and second segments which are arranged alternately in an extending direction of the first data line, the first segments are arranged in a same layer as a source and drain of the thin film transistor, the second segments are arranged in a same layer as a gate of the thin film transistor, and each first segment is electrically connected with an adjacent second segment through a second electrically connecting part.

2. The array substrate of claim 1 , wherein, the second data line is arranged in a same layer as the source and drain of the thin film transistor.

3. The array substrate of claim 2 , wherein,
each first segment of the first data line is provided with fourth via holes which are arranged at both ends of each first segment in the extending direction of the first data line, and penetrate a passivation layer of the thin film transistor;
each second segment of the first data line is provided with fifth via holes which are arranged at both ends of the second segment in the extending direction of the first data line, and penetrate a gate insulating layer and the passivation layer; and
the second electrically connecting part is electrically connected with each first segment of the first data line and the second segment adjacent with the first segment, through the fourth via holes and the fifth via holes.

4. The array substrate of claim 1 , wherein,
the second electrically connecting part is arranged in a same layer as the pixel electrode of each sub-pixel unit.

5. The array substrate of claim 1 , wherein,
the second data line comprises first segments and second segments which are arranged alternately in an extending direction of the second data line;
the first segments of the second data line and the first segments of the first data line are arranged side by side, and are arranged in a same layer as the gate of the thin film transistor;
the second segments of the second data line and the second segments of the first data line are arranged side by side, and are arranged in a same layer as the source and drain of the thin film transistor; and
the first segments of the second data line are electrically connected with the second segments of the second data line through a third electrically connecting part.

6. The array substrate of claim 5 , wherein,
each first segment of the second data line is provided with sixth via holes at both ends in the extending direction of the second data line, and the sixth via holes penetrate a gate insulating layer and a passivation layer of the thin film transistor;
each second segment of the second data line is provided with seventh via holes at both ends in the extending direction of the second data line, and the seventh via holes penetrate the passivation layer; and
the third electrically connecting part electrically connects each first segment of the second data line with the second segment adjacent with the first segment, through the sixth via holes and the seventh via holes.

7. The array substrate of claim 5 , wherein,
the third electrically connecting part is arranged in a same layer as the pixel electrode of each sub-pixel unit.

8. A display panel, comprising the array substrate of claim 1 .

9. A display device, comprising the display panel of claim 8 .

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Wang Shoukun
• Guo Huibin
• Feng Yuchun
• Li Liangliang
• Kuo Tsungchieh

Classifications

• H01L27/124

  Electricity · mapped topic

• G02F2201/123

  pixel · CPC title

• H01L27/127

  Electricity · mapped topic

• G02F2001/134345

  Physics · mapped topic

• G02F1/134309

  characterised by their geometrical arrangement · CPC title