Manufacture method of low temperature poly-silicon array substrate

Patent metadata

Field	Value
Publication number	US-10101620-B2
Application number	US-201615111822-A
Country	US
Kind code	B2
Filing date	May 20, 2016
Priority date	Jan 28, 2016
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

The present invention provides a manufacture method of a Low Temperature Poly-silicon array substrate. A halftone mask is utilized to realize the pattern process to the polysilicon layer and the N type heavy doping process of the polysilicon section of the NMOS region. In comparison with prior art, one mask is eliminated, and thus, the production cost is reduced, and the manufactured Low Temperature Poly-silicon array substrate possesses fine electronic property.

First claim

What is claimed is:

1. A manufacture method of a Low Temperature Poly-silicon array substrate, comprising steps of:
step 1, providing a substrate, and defining a NMOS region and a PMOS region on the substrate, and depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a first light shielding layer in the NMOS region and a second light shielding layer in the PMOS region;
step 2, forming a buffer layer on the first light shielding layer, the second light shielding layer and the substrate, and depositing an amorphous silicon layer on the buffer layer, and employing a low temperature crystallization process to convert the amorphous silicon layer into a polysilicon layer, and employing a mask to implement a channel doping to the polysilicon layer in the NMOS region;
step 3, coating a photoresist layer on the polysilicon layer, and after employing a halftone mask to implement exposure, development to the photoresist layer, a first photoresist layer in the NMOS region and a second photoresist layer in the PMOS region are obtained, and the first photoresist layer comprises a thick layer region in the middle and thin layer regions at two sides of the thick layer region, and a thickness of the second photoresist layer is uniform, and thicknesses of the thick layer region of the first photoresist layer and the second photoresist layer are equal;
employing the first photoresist layer and the second photoresist layer for shielding to etch the polysilicon layer to respectively obtain a first polysilicon section in the NMOS region and a second polysilicon section in the PMOS region;
employing a dry etching apparatus to implement ashing treatment to the first photoresist layer and the second photoresist layer to completely remove the thin layer regions at the two sides on the first photoresist layer, and meanwhile, to make the thicknesses of the thick layer of the first photoresist layer and the second photoresist layer thinner; employing remained thick layer region on the first photoresist layer and the second photoresist layer to be a mask to implement N type heavy doping to the two sides of the first polysilicon section to obtain two N type heavy doping regions;
step 4, depositing a gate isolation layer on the first polysilicon section, the second polysilicon section and the buffer layer, and depositing a second metal layer on the gate isolation layer, and patterning the second metal layer to obtain a first gate and a second gate correspondingly above the first polysilicon section and the second polysilicon section, respectively;
employing the first gate to be a mask to implement N type light doping to the first polysilicon section to obtain two N type light doping regions respectively at inner sides of the two N type heavy doping regions, and a first channel region is formed in a region between the two N type heavy doping regions on the first polysilicon section;
step 5, employing a mask to implement P type heavy doping to two sides of the second polysilicon section to obtain two P type heavy doping regions, and a second channel region is formed in a region between the two P type heavy doping regions on the second polysilicon section;
step 6, depositing an interlayer insulation layer on the first gate, the second gate and the gate isolation layer, and patterning the interlayer insulation layer and the gate isolation layer to obtain a first via above the N type heavy doping region and a second via above the P type heavy doping region, and then implementing dehydrogenation and activation treatments to the interlayer insulation layer;
step 7, depositing a third metal layer on the interlayer insulation layer, and patterning the third metal layer to obtain a first source, a first drain, a second source and a second drain, and the first source and the first drain respectively contact with the N type heavy doping region through the first via, and the second source and the second rain respectively contact with the P type heavy doping region through the second via;
step 8, forming a flat layer on the first source, the first drain, the second source, the second drain and the interlayer insulation layer, and patterning the flat layer to obtain a third via above the first drain;
step 9, depositing a first transparent conductive oxide layer on the flat layer, and patterning the first transparent conductive oxide layer to obtain a common electrode;
step 10, depositing a passivation protective layer on the common electrode and the flat layer, and the passivation protective layer covers the third via on the flat layer, and then patterning the passivation protective layer to obtain a fourth via at a bottom of the third via on the passivation protective layer;
step 11, depositing a second transparent conductive oxide layer on the passivation protective layer, and patterning the second transparent conductive oxide layer to obtain a pixel electrode, and the pixel electrode contacts with the first drain through the fourth via.

2. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 1 , wherein in the step 2, the low temperature crystallization process is Excimer Laser Annealing or Metal-Induced Lateral Crystallization.

3. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 1 , wherein in the step 2, a specific operation of channel doping is: coating a photoresist layer on the polysilicon layer, and employing a mask to implement exposure, development to the photoresist layer, and after removing the photoresist layer in the NMOS region, implementing P type light doping to the polysilicon layer in the entire NMOS region.

4. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 1 , wherein in the step 6, rapid thermal annealing is employed to implement the dehydrogenation and activation treatments to the interlayer insulation layer.

5. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 1 , wherein the substrate is a glass substrate; material of the first metal layer, the second metal layer and the third metal layer is a stack combination of one or more of molybdenum, titanium, aluminum and copper; the buffer layer, the gate isolation layer, the interlayer insulation layer and the passivation protective layer are Silicon Oxide layers, Silicon Nitride layers or composite layers superimposed with Silicon Oxide layers and Silicon Nitride layers; the flat layer is organic photoresist material.

6. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 1 , wherein material of the first transparent conductive oxide layer and the second transparent conductive oxide layer is metal oxide.

7. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 6 , wherein the metal oxide is Indium Tin Oxide, Aluminum Tin Oxide, Aluminum Zinc Oxide or Indium Germanium Zinc Oxide.

8. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 1 , wherein the ion doped by the N type heavy doping and the N type light doping is phosphorus ion or arsenic ion.

9. The manufacture method of the Low Temperature Poly-silicon array substrate according to claim 3 , wherein the ion doped by the P type heavy doping and the P type light doping is boron ion or gallium ion.

10. A manufacture method of a Low Temperature Poly-silicon array substrate, comprising steps of:
step 1, providing a substrate, and defining a NMOS region and a PMOS region on the substrate, and depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a first light shielding laye

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Deng si
• Guo Yuan

Classifications

• H10P14/3802 Primary

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10D84/01 Primary

  Manufacture or treatment · CPC title

• G02F1/1362 Primary

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title

• G02F2202/104

  poly-Si · CPC title