Space transformation methods

Patent metadata

Field	Value
Publication number	US-10101381-B2
Application number	US-201213600460-A
Country	US
Kind code	B2
Filing date	Aug 31, 2012
Priority date	Aug 31, 2012
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A test system includes a test printed circuit board (PCB), a flip chip package mounted on the PCB, one or more test probes coupled to the flip chip package and a first integrated circuit (IC) coupled to the test probes to enable testing of the first IC using electrical circuitry of the flip chip package.

First claim

What is claimed is:

1. A test system comprising:
a test printed circuit board (PCB); and
a multi-chip package mounted on the test PCB, comprising:
a flip chip package;
one or more test probes having a first end coupled to the flip chip package;
a central processing unit (CPU) integrated circuit (IC) coupled to a second end of the test probes to enable testing of the first product IC using electrical circuitry of the flip chip package; and
a chipset IC mounted on the flip chip package to communicate with the CPU IC during testing of the CPU IC via routing between the first product IC and the chipset IC.

2. The test system of claim 1 wherein the flip chip package includes routing to enable the communications with the chipset IC.

3. The test system of claim 1 wherein communications between the CPU IC and the chipset IC is performed through the test probes.

4. The test system of claim 1 wherein the CPU IC is mounted on the chipset IC.

5. The test system of claim 4 wherein the test probes are coupled to the flip chip package by directly connecting to Through Silicon Via (TSV) pads of the chipset IC.

6. A method comprising:
mounting a flip chip package included in a multi-chip package on a test printed circuit board (PCB);
coupling a first end of one or more test probes to the flip chip package; and
coupling central processing unit (CPU) included in the multi-chip package to a second end of the test probes to enable testing of the CPU IC using electrical circuitry of the flip chip package;
mounting a chipset IC included in the multi-chip package on the flip chip package; and
testing the CPU IC via communications with the chipset IC.

7. The method of claim 6 wherein the flip chip package includes routing to enable the communications with the chipset IC.

8. The method of claim 7 wherein communications between the CPU IC is and the chipset IC is performed through the test probes.

9. The method of claim 6 further comprising mounting the CPU IC on the chipset IC.

10. The method of claim 9 wherein the test probes are coupled to the flip chip package by connecting directly to Through Silicon Via (TSV) of the chipset IC.

Assignees

• Acar Erkan
• Tadayon Pooya
• Balian Armen Y
• Caughey Ethan
• Intel Corp

Inventors

• Acar Erkan
• Tadayon Pooya
• Balian Armen Y
• Caughey Ethan

Classifications

• G01R31/2607 Primary

  Circuits therefor (G01R31/2642 takes precedence) · CPC title

• Y10T29/49128

  Assembling formed circuit to base · CPC title

• G01R31/2889 Primary

  Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence) · CPC title

• G01R1/07378

  using an intermediate adapter, e.g. space transformers (G01R1/07371 takes precedence) · CPC title

• Y10T29/49004

  including measuring or testing of device or component part · CPC title