Synchronous detection circuit and method for extracting magnitude and phase from a waveform

Patent metadata

Field	Value
Publication number	US-10101371-B2
Application number	US-201615258399-A
Country	US
Kind code	B2
Filing date	Sep 7, 2016
Priority date	Sep 7, 2016
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

First claim

What is claimed is:

1. A synchronous detection circuit, comprising:
a driver circuit configured to be coupled to a load, the driver circuit supplying an input waveform at an input frequency to the load;
an analog-to-digital converter (ADC) configured to be coupled to the load, the ADC receiving an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform; and
a controller coupled to the ADC, the controller configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, wherein the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform.

2. The synchronous detection circuit as recited in claim 1 , wherein the ADC is configured for generating the digital samples and the sub-samples in synchronization with a clock signal having a fixed clock frequency, and wherein the integer number, M, of sub-samples is proportional to the fixed clock frequency and inversely proportional to the input frequency of the input waveform.

3. The synchronous detection circuit as recited in claim 2 , wherein the integer number, M, of sub-samples is substantially equal to the fixed clock frequency divided by 4N times the input frequency, where N is an integer number greater than or equal to 1.

4. The synchronous detection circuit as recited in claim 1 , wherein the controller is configured for setting the OSR of the ADC equal to an integer multiple of the integer number, M, wherein the input frequency of the input waveform is programmable and selected from a range of input frequencies, and wherein the integer multiple changes with changes in input frequency.

5. The synchronous detection circuit as recited in claim 4 , wherein the controller is configured for setting the OSR of the ADC equal to N times M for input frequencies of 20 kHz and above, where N is an integer number greater than or equal to 1.

6. The synchronous detection circuit as recited in claim 4 , wherein the controller is configured for setting the OSR of the ADC equal to N times M divided by X, where X is an integer number greater than or equal to 2, for input frequencies below 20 kHz.

7. The synchronous detection circuit as recited in claim 4 , wherein the controller is further configured for setting a decimation rate (DR) of the ADC equal to the OSR.

8. The synchronous detection circuit as recited in claim 7 , wherein the controller is configured for using a table of values to set the OSR and the DR of the ADC, wherein the table of values comprises predetermined values of M, N and OSR for each input frequency within the range of input frequencies.

9. The synchronous detection circuit as recited in claim 8 , further comprising a memory component configured for storing the table of values.

10. The synchronous detection circuit as recited in claim 1 , wherein the controller is further configured for using the four digital samples to extract magnitude and phase values from the output waveform for every period of the output waveform.

11. The synchronous detection circuit as recited in claim 1 , wherein the controller is further configured for averaging the four digital samples over a number, P, of periods of the output waveform, and further configured for using the averaged digital samples to extract magnitude and phase values from the output waveform for every P periods of the output waveform.

12. A method, comprising:
supplying an input waveform at an input frequency to a load;
receiving an output waveform from the load, wherein the output waveform comprises four quadrants for each period of the output waveform;
oversampling the output waveform so as to generate an integer number, M, of sub-samples for each quadrant of the output waveform, wherein the integer number, M, is inversely proportional to the input frequency of the input waveform; and
decimating the integer number, M, of sub-samples so as to generate four digital samples per period of the output waveform, such that one digital sample is generated within each quadrant.

13. The method as recited in claim 12 , further comprising using the four digital samples to extract magnitude and phase values from the output waveform for every period of the output waveform.

14. The method as recited in claim 12 , further comprising averaging the four digital samples generated over a number, P, of periods of the output waveform, and using the averaged digital samples to extract magnitude and phase values from the output waveform for every P periods of the output waveform.

15. The method as recited in claim 12 , wherein prior to the steps of oversampling and decimating, the method further comprises setting an oversampling rate (OSR) equal to a decimating rate (DR) of an analog-to-digital converter (ADC) configured for generating the sub-samples and the digital samples.

16. The method as recited in claim 15 , wherein the step of the setting the OSR and the DR of the ADC comprises setting the OSR and the DR equal to an integer multiple of the integer number, M, wherein the input frequency of the input waveform is programmable and selectable from a range of input frequencies, and wherein the integer multiple changes with changes in input frequency.

17. The method as recited in claim 16 , wherein the step of the setting the OSR and the DR of the ADC comprises setting the OSR and the DR equal to N times M for a first subset of input frequencies within the range of input frequencies, where N is an integer number greater than or equal to 1.

18. The method as recited in claim 16 , wherein the step of the setting the OSR and the DR of the ADC comprises setting the OSR equal to N times M divided by X, where X is an integer number greater than or equal to 2, and setting the DR equal to N times M for a second subset of input frequencies within the range of input frequencies.

19. The method as recited in claim 15 , further comprising supplying a clock signal having a fixed clock frequency to the ADC for generating the integer number, M, of sub-samples in synchronization with the clock signal, such that the integer number, M, is proportional to the fixed clock frequency and inversely proportional to the input frequency of the input waveform.

20. The method as recited in claim 19 , wherein the integer number, M, of sub-samples is substantially equal to the fixed clock frequency divided by 4N times the input frequency, where N is an integer number greater than or equal to 1.

Assignees

• Silicon Lab Inc

Inventors

• Cherkassky Alexander
• Del Signore Bruce P

Classifications

• G01R25/005

  Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal · CPC title

• G01R27/00 Primary

  Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom · CPC title

• A61B5/0537

  Measuring body composition by impedance, e.g. tissue hydration or fat content · CPC title

• A61B5/7278

  Artificial waveform generation or derivation, e.g. synthesizing signals from measured signals · CPC title

• G01N27/04

  by investigating resistance · CPC title