Printed circuit board with edge soldering for high-density packages and assemblies

US10098241B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10098241-B2
Application numberUS-201514921749-A
CountryUS
Kind codeB2
Filing dateOct 23, 2015
Priority dateOct 23, 2015
Publication dateOct 9, 2018
Grant dateOct 9, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention is notably directed to a printed circuit board, or PCB. This PCB has two main surfaces, each delimited by lateral edges, as well as lateral surfaces, each meeting each of the two main surfaces at one lateral edge. The present PCB further comprises a row of solder pads, which extends along a lateral edge of the PCB. Each solder pad is formed directly at the lateral edge and/or directly on a lateral surface (meeting one of the two main surfaces at said lateral edge). I.e., each pad interrupts a lateral edge and/or an adjoining lateral surface. One or more chips, e.g., memory chips, can be mounted on such a PCB to form an IC package. The above solder pad arrangement allows particularly dense arrangements of IC packages to be obtained. The present invention is further directed to related devices and methods of fabrication thereof.

First claim

Opening claim text (preview).

The invention claimed is: 1. An integrated circuit assembly, or IC assembly, comprising at least two IC packages, each according to the IC package including a printed circuit board (PCB) and an integrated circuit chip, or IC chip, mounted on the PCB, the PCB comprising: two opposite main surfaces, each delimited by lateral edges; and lateral surfaces, each meeting each of the main surfaces at one of the lateral edges, the PCB further comprising: a row of solder pads extending along a lateral edge of the PCB, with each solder pad of the row formed directly at said lateral edge and/or directly on one of the lateral surfaces meeting one of the two main surfaces at said lateral edge; and a main surface of the IC chip facing and electrically connecting one of the two main surfaces of the PCB, and a main surface of one of the at least two IC packages parallel to and facing a main surface of another one of the at least two IC packages, wherein each PCB of the at least two IC packages is edge-soldered to a same board via a respective row of solder pads formed directly at a lateral edge and/or directly on one lateral surface of said each PCB, and said IC assembly further comprising: a third integrated circuit package, or third IC package, between each of said at least two IC packages, wherein the third integrated circuit package comprises a printed circuit board, or PCB, and an integrated circuit chip, or IC chip, mounted on the PCB of the third IC package, a main surface of the IC chip of the third IC package facing and electrically connecting a main surface of the PCB of the third IC package, and a heat dissipating structure comprising one or more thermally conducting layers, each intercalated between an IC package and an adjacent IC package of the IC assembly, wherein one thermally conducting layer provides mechanical and direct thermal contact with a surface of an IC chip of a first IC package and a main non-conducting surface of the adjacent IC package. 2. The PCB of claim 1 , wherein each solder pad of the row is on said one of the two main surfaces and is at least partly housed in a hole cut open at said one of the lateral surfaces, said hole being a blind hole or a through hole. 3. The PCB of claim 2 , wherein each solder pad of the row comprises a blind hole plated, on said one of the two main surfaces, with an electrically conductive material. 4. The PCB of claim 3 , wherein said row of solder pads is a first row, and said lateral edge is a first lateral edge, the PCB further comprising a second row of solder pads on the opposite one of the two main surfaces, the second row extending opposite to the first row, along a second lateral edge of the PCB, each solder pad of the second row formed on the second lateral edge and comprising a blind hole plated, on said opposite one of the two main surfaces, with an electrically conductive material. 5. The PCB of claim 2 , wherein each solder pad of the row comprises a through hole filled or plated with an electrically conductive material, so as to enable an electrical connection from said one of the lateral surfaces. 6. The integrated circuit package of claim 1 , wherein the IC chip is a memory chip. 7. The integrated circuit package of claim 1 , wherein the IC package comprises two or more IC chips, each mounted on the PCB, a main surface of each of the IC chips facing and electrically connecting one of the two main surfaces of the PCB. 8. The IC assembly of claim 1 , wherein said same board is a baseboard, a sideboard or a daughterboard of the IC assembly. 9. The IC assembly of claim 1 , wherein said third IC package is an IC package including a PCB having two opposite main surfaces, each delimited by lateral edges, and lateral surfaces, each meeting each of the main surfaces at one of the lateral edges, the PCB comprising: a row of solder pads extending along a lateral edge of the PCB, with each solder pad of the row formed directly at said lateral edge and/or directly on one of the lateral surfaces meeting one of the two main surfaces at said lateral edge; and an integrated circuit chip, or IC chip, mounted on the PCB, a main surface of the IC chip facing and electrically connecting one of the two main surfaces of the PCB, the third IC package being soldered to said same board via a row of solder pads of the PCB of the third IC package, the row of solder pads formed directly at a lateral edge of the PCB of the third IC package and/or directly on a lateral surface of the PCB of the third IC package. 10. The IC assembly of claim 1 , wherein said thermally conducting plates are, each, thermally conducting foils. 11. The IC assembly of claim 10 , wherein the heat dissipating structure further comprises: a rigid structure in thermal communication with the thermally conducting layers, the latter being flexible foils, wherein each of the foils is bent so as for one portion of the foils to cover a main surface of the IC chip of one of the two neighboring IC packages, and a bent portion of the foils to be sandwiched between said lateral surface of the IC chip and said rigid structure. 12. The IC assembly of claim 1 , wherein the PCB of the third IC package is electrically connected to a PCB of one or each of said at least two IC packages via a flexible portion of a PCB. 13. The IC assembly of claim 12 , wherein said flexible portion is folded around one of the thermally conducting layers.

Assignees

Inventors

Classifications

  • substantially perpendicularly to each other (H05K3/361 takes precedence) · CPC title

  • One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters (H05K1/142 and H05K1/147 take precedence) · CPC title

  • H05K3/403Primary

    Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof (H05K3/4092 takes precedence) · CPC title

  • Folded back on itself · CPC title

  • Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers · CPC title

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Frequently asked questions

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What does patent US10098241B2 cover?
The present invention is notably directed to a printed circuit board, or PCB. This PCB has two main surfaces, each delimited by lateral edges, as well as lateral surfaces, each meeting each of the two main surfaces at one lateral edge. The present PCB further comprises a row of solder pads, which extends along a lateral edge of the PCB. Each solder pad is formed directly at the lateral edge and…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H05K3/403. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 09 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).