Use of combined masking techniques and/or combined material removal techniques to protectively coat electronic devices

US10098236B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10098236-B2
Application numberUS-201514836875-A
CountryUS
Kind codeB2
Filing dateAug 26, 2015
Priority dateAug 26, 2014
Publication dateOct 9, 2018
Grant dateOct 9, 2018

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Processes for masking electronic devices, including, but not limited to, electronic subassemblies, prior to the application of protective coatings to the electronic devices are disclosed. Such processes include the use of a plurality of different masking techniques in combination to mask the electronic device. Different masking techniques may be used to mask different features and/or components of the electronic device. Some features and/or components may be masked by way of two or more masking techniques. With one or more masks in place, an electronic device may be protectively coated. After a protective coating has been applied to the electronic device, at least a portion of the mask(s) may be removed from the electronic device. Protectively coated electronic devices may then be assembled with one another.

First claim

Opening claim text (preview).

What is claimed: 1. A method for applying a protective coating to an electronic device, comprising: applying a protective coating to selected areas of an electronic device comprising features and components, wherein applying the protective coating to the selected areas of the electronic device comprises masking the electronic device in areas of the electronic device other than the selected areas, coating the electronic device and de-masking the electronic device, wherein the masking the electronic device includes: applying flat preformed elements to flat features and/or components of the electronic device; applying a fluid masking material to at least some of the features and/or the components of the electronic device that protrude from the electronic device: and applying a non-hardenable semisolid masking material around at least one of said components that protrudes from a daughter board of the electronic device and/or within a receptacle of at least one of the components carried by the electronic device. 2. The method of claim 1 , further comprising applying a second protective coating to selected areas of a motherboard of the electronic device, wherein applying the second protective coating to selected areas of the motherboard comprises masking the motherboard, coating the motherboard and de masking the motherboard. 3. The method of claim 2 , wherein masking the motherboard includes applying a fluid masking material to at least one electrical connector carried by the motherboard. 4. The method of claim 1 , further comprising applying a third protective coating to selected areas of the daughter board of the electronic device, wherein applying the third protective coating to selected areas of the daughter board comprises masking the daughter board, coating the daughter board and de-masking the daughter board. 5. The method of claim 4 , wherein masking the daughter board includes applying flat preformed elements to flat features and/or components of the daughterboard and applying a fluid masking material to at least some features and/or components that protrude from the daughter board. 6. The method of claim 5 , wherein masking the daughter board further includes applying a non-hardenable semisolid masking material around at least one component that protrudes from the daughter board and/or within a receptacle of at least one component carried by the daughter board. 7. The method of claim 1 , wherein applying the non-hardenable semisolid masking material comprises applying the non-hardenable semisolid masking material to a zero insertion force connector. 8. The method of claim 1 , further comprising applying a fourth protective coating to selected areas of a flexible printed circuit connector of the electronic device, wherein applying the fourth protective coating to selected areas of the flexible printed circuit connector comprises masking the flexible printed circuit connector, coupling the flexible printed circuit connector to a complementary element of an electrical connector, and coating the flexible printed circuit connector and the complementary element.

Assignees

Inventors

Classifications

  • H10W74/01Primary

    Manufacture or treatment · CPC title

  • Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices · CPC title

  • Processes for applying liquids or other fluent materials to surfaces to obtain special surface effects, finishes or structures · CPC title

  • Temporary protective insulating layer · CPC title

  • provided with connectors and printed circuit boards [PCB], e.g. automotive electronic control units · CPC title

Patent family

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Frequently asked questions

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What does patent US10098236B2 cover?
Processes for masking electronic devices, including, but not limited to, electronic subassemblies, prior to the application of protective coatings to the electronic devices are disclosed. Such processes include the use of a plurality of different masking techniques in combination to mask the electronic device. Different masking techniques may be used to mask different features and/or components…
Who is the assignee on this patent?
Hzo Inc
What technology area does this patent fall under?
Primary CPC classification H10W74/01. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 09 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).