Read-out integrated circuit with integrated compressive sensing

Patent metadata

Field	Value
Publication number	US-10097774-B2
Application number	US-201515322633-A
Country	US
Kind code	B2
Filing date	Jul 10, 2015
Priority date	Jul 12, 2014
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

According to one aspect, a Read-Out Integrated Circuit (ROIC) with integrated Compressive Sampling (CS) is provided. The ROIC includes an input to couple to a photodetector array including a plurality of photodetectors and is configured to generate compressed image data by sampling and summing the values of the plurality of photodetectors consistent with a set of Compressive Sampling Measurement Matrices and provide the resulting coded aggregates to a signal processor as compressed image data.

First claim

What is claimed is:

1. A Read-Out Integrated Circuit (ROIC) with integrated Compressive Sampling (CS) configured to couple to a photodetector array including a plurality of photodetectors, the ROIC comprising:
a mask generator and control component configured to generate a plurality of Compressive Sampling Measurement Matrices (CSMMs) each descriptive of a sampling pattern to sample at least one portion of the photodetector array; and
a compute element array coupled to the photodetector array and the mask generator and control component, the compute element array configured to:
receive a plurality of photodetector values from the photodetector array;
receive the CSMMs from the mask generator and control component;
generate compressed image data by selectively sampling, in parallel, a plurality of portions of the photodetector array consistent with the plurality of CSMMs, wherein each of the CSMMs specify selected photodetector values to be sampled within a corresponding portion of the plurality of portions, and the compressed image data includes a plurality of coded aggregates; and
provide the compressed image data to at least one processor.

2. The ROIC according to claim 1 , wherein the compute element array includes a plurality of compute elements each including a memory coupled to a logic core.

3. The ROIC according to claim 2 , wherein the memory includes 2-port static random access memory (SRAM).

4. The ROIC according to claim 2 , wherein the memory stores the compressed image data and the logic core is configured to determine the compressed image data.

5. The ROIC according to claim 2 , further comprising a block mapping component configured to direct at least one portion of the plurality of photodetector values to each compute element of the plurality of compute elements.

6. The ROIC according to claim 1 , wherein the mask generator and control component includes at least one of a pseudo-random number generator and a unique-random number generator.

7. The ROIC according to claim 1 , wherein the mask generator and control component includes a memory and wherein the mask generator and control component generates the plurality of CSMMs at least in part by reading at least one stored CSMM from the memory.

8. The ROIC according to claim 1 , wherein one or more portions of the plurality of portions of the photodetector array have a compression rate of one.

9. The ROIC according to claim 1 , further comprising an analog-to-digital converter (ADC) coupled to the compute element array and configured to digitize the plurality of photodetector values received from the photodetector array.

10. The ROIC according to claim 1 , wherein each CSMM of the plurality of CSMMs includes at least one of a decimal zero, a decimal one, and a decimal negative one.

11. The ROIC according to claim 1 , wherein the plurality of photodetectors includes a plurality of digital pixels and wherein the plurality of photodetector values includes a plurality of pixel values.

12. The ROIC according to claim 1 , wherein each coded aggregate of the plurality of coded aggregates is a sum of the photodetector values specified by one CSMM of the plurality of CSMMs.

13. A focal plane array (FPA) imaging system comprising:
at least one processor;
a photodetector array including a plurality of photodetectors; and
a Read-Out Integrated Circuit (ROIC) with integrated Compressive Sampling (CS) coupled between the at least one processor and the photodetector array, the ROIC being configured to:
generate a plurality of Compressive Sampling Measurement Matrices (CSMMs) each descriptive of a sampling pattern to sample at least one portion of the plurality of photodetectors,
generate compressed image data by selectively sampling, in parallel, a plurality of portions of the plurality of photodetectors consistent with the plurality of CSMMs, wherein each of the CSMMs specify photodetector values to be sampled within a corresponding portion of the plurality of portions, and the compressed image data includes a plurality of coded aggregates, and
output the compressed image data to the at least one processor.

14. The system according to claim 13 , wherein the photodetector array includes a plurality of digital pixels.

15. The system according to claim 13 , wherein the ROIC includes a mask generator and control component configured to generate the plurality of CSMMs.

16. The system according to claim 15 , wherein the mask generator and control component includes at least one of a pseudo-random number generate and a unique-random number generator.

17. The system according to claim 13 , wherein the ROIC includes a compute element array configured to generate the compressed image data including a memory coupled to a logic core.

18. The system according to claim 13 , further comprising an image reconstruction engine configured to instruct the at least one processor to reconstruct at least one image based on the compressed image data.

19. The system according to claim 13 , wherein each coded aggregate of the plurality of coded aggregates is a sum of the photodetector values specified by one CSMM of the plurality of CSMMs.

Assignees

• Gibbons Robert C
• Denham Martin S
• Beuville Eric J
• Fluckiger David U
• Raytheon Co

Inventors

• Gibbons Robert C
• Denham Martin S
• Beuville Eric J
• Fluckiger David U

Classifications

• H03M7/3062 Primary

  Compressive sampling or sensing · CPC title

• H04N5/919

  by dividing samples or signal segments, e.g. television lines, among a plurality of recording channels · CPC title

• H04N25/44

  by partially reading an SSIS array · CPC title

• H04N25/46 Primary

  by combining or binning pixels · CPC title

• G06V10/513

  Sparse representations · CPC title