Add/drop multiplexer and method for processing signal in add/drop multiplexer

US10097305B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10097305-B2
Application numberUS-201715782745-A
CountryUS
Kind codeB2
Filing dateOct 12, 2017
Priority dateApr 16, 2015
Publication dateOct 9, 2018
Grant dateOct 9, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

The present application discloses an add/drop multiplexer, including a first line board and a tributary board, where the first line board includes at least a first interface and a second interface, the first interface is disposed between the tributary board and the first line board, and the second interface is disposed on a network side of the first line board; the first line board is configured to output a first signal received from a first link through the second interface; the first line board is configured to output a second signal received from the first link to the tributary board through the first interface; and the first line board is configured to receive a third signal from the tributary board through the first interface, and input the third signal into the first link. An inter-board interface on a link is effectively eliminated, thereby improving a link bandwidth of a device.

First claim

Opening claim text (preview).

What is claimed is: 1. An add/drop multiplexer, comprising: a tributary board; and a first line board comprising at least a first interface and a second interface, the first interface is disposed between the tributary board and the first line board, and the second interface is disposed on a network side of the first line board, and wherein the first line board is configured to: receive a first signal from a first link, and output the first signal through the second interface, receive a second signal from the first link, and output the second signal to the tributary board through the first interface, and receive a third signal from the tributary board through the first interface, and input the third signal into the first link. 2. The add/drop multiplexer according to claim 1 , further comprising: a second line board comprising at least a third interface and a fourth interface, the third interface is disposed between the tributary board and the second line board, and the fourth interface is disposed on a network side of the second line board, and wherein the second line board is configured to: receive a fourth signal from a second link, and output the fourth signal through the fourth interface; receive a fifth signal from the second link, and output the fifth signal to the tributary board through the third interface; and receive a sixth signal from the tributary board through the third interface, and input the sixth signal into the second link. 3. The add/drop multiplexer according to claim 1 , wherein the tributary board is disposed on either side of the first line board and the second line board. 4. The add/drop multiplexer according to claim 1 , wherein the tributary board is disposed on a same side of the first line board and the second line board. 5. The add/drop multiplexer according to claim 1 , wherein: the tributary board further comprises a combiner/selector and a replicator/distributor; and the tributary board is configured to: receive the second signal from the first line board, generate a downlink service by using the combiner/selector, send the downlink service to a client device, receive an uplink service from the client device, generate the third signal by using the replicator/distributor, and input the third signal into the first line board. 6. The add/drop multiplexer according to claim 1 , further comprising: a third line board having a combiner/selector and a replicator/distributor of the tributary board integrated into the third line board, and comprising at least a fifth interface and a sixth interface, the fifth interface is disposed between the first line board and the third line board, and the sixth interface is disposed on a network side of the third line board, and wherein the third line board is configured to: receive a seventh signal from a third link, and output the seventh signal through the sixth interface; receive an eighth signal from the third link; output, to the first line board through the fifth interface, the eighth signal after the eighth signal passes through the replicator/distributor; receive a ninth signal from the first line board through the fifth interface; and input the ninth signal into the third link by using the combiner/selector. 7. A method for processing a signal in an add/drop multiplexer, the method comprising: receiving, by a first line board, a first signal from a first link, and outputting the first signal through a second interface, wherein the second interface is disposed on a network side of the first line board; receiving, by the first line board, a second signal from the first link, and outputting the second signal to a tributary board through a first interface, wherein the first interface is disposed between the tributary board and the first line board; and receiving, by the first line board, a third signal from the tributary board through the first interface, and inputting the third signal into the first link. 8. The method according to claim 7 , further comprising: receiving, by a second line board, a fourth signal from a second link, and outputting the fourth signal through a fourth interface, wherein the fourth interface is disposed on a network side of the second line board; receiving, by the second line board, a fifth signal from the second link, and outputting the fifth signal to the tributary board through a third interface, wherein the third interface is disposed between the tributary board and the second line board; and receiving, by the second line board, a sixth signal from the tributary board through the third interface, and inputting the sixth signal into the second link. 9. The method according to claim 7 , wherein: receiving, by the tributary board, the second signal from the first line board; generating, a downlink service using a combiner/selector on the tributary board, and sending the downlink service to a client device; and receiving, by the tributary board, an uplink service from the client device; generating the third signal using a replicator/distributor on the tributary board, and inputting the third signal into the first line board. 10. The method according to claim 7 , further comprising: receiving, by a third line board, a seventh signal from a third link, and outputting the seventh signal through a sixth interface, wherein the sixth interface is disposed on a network side of the third line board; receiving, by the third line board, an eighth signal from the third link, and outputting, to the first line board through a fifth interface, the eighth signal after the eighth signal passes through a replicator/distributor, wherein the fifth interface is disposed between the first line board and the third line board; and receiving, by the third line board, a ninth signal from the first line board through the fifth interface, and inputting the ninth signal into the third link by using a combiner/selector.

Assignees

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Classifications

  • Monitoring arrangements {(for SDH/SONET rings H04J3/085)} · CPC title

  • Constructional details of switching devices · CPC title

  • Signalling aspects · CPC title

  • Provisions for the electrical-optical layer interface · CPC title

  • Architecture aspects · CPC title

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What does patent US10097305B2 cover?
The present application discloses an add/drop multiplexer, including a first line board and a tributary board, where the first line board includes at least a first interface and a second interface, the first interface is disposed between the tributary board and the first line board, and the second interface is disposed on a network side of the first line board; the first line board is configure…
Who is the assignee on this patent?
Huawei Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H04J14/0215. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 09 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).