High-speed receiver architecture

Patent metadata

Field	Value
Publication number	US-10097273-B2
Application number	US-201715839380-A
Country	US
Kind code	B2
Filing date	Dec 12, 2017
Priority date	Oct 3, 2005
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

First claim

What is claimed is:

1. A receiver comprising:
an analog-to-digital converter (ADC) that generates signal samples from a received signal having combined non-Gaussian noise and Gaussian noise;
wherein the ADC is a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
a 1-bit comparator coupled to the input track-and-hold stage,
a 1-bit digital-to-analog converter (DAC) coupled to the 1-bit comparator,
an analog subtractor coupled to the 1-bit DAC and the input track-and-hold stage,
a residue amplifier coupled to the analog subtractor, and
a track-and-hold circuit coupled to the residue amplifier;

a feedforward equalizer coupled to receive the signal samples from the ADC, and to apply equalization to generate equalized samples;
a decoder coupled to an output of the feedforward equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal; and
a channel estimator to receive the output of the feedforward equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the feedforward equalizer based on the error feedback signal;
wherein the ADC is configured in a sub-radix architecture having more ADC stages than there are bits in the received signal.

2. The receiver of claim 1 wherein the residue amplifiers of the ADC stages include open-loop amplifiers.

3. A receiver comprising:
an analog-to-digital converter (ADC) that generates signal samples from a received signal having combined non-Gaussian noise and Gaussian noise;
wherein the ADC is a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
a 1-bit comparator coupled to the input track-and-hold stage,
a 1-bit digital-to-analog converter (DAC) coupled to the 1-bit comparator,
an analog subtractor coupled to the 1-bit DAC and the input track-and-hold stage,
a residue amplifier coupled to the analog subtractor, and
a track-and-hold circuit coupled to the residue amplifier;

a feedforward equalizer coupled to receive the signal samples from the ADC, and to apply equalization to generate equalized samples;
a decoder coupled to an output of the feedforward equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal; and
a channel estimator to receive the output of the feedforward equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the feedforward equalizer based on the error feedback signal;
wherein the cumulative metric is approximated by
M≈Σ n [(ŷ n ) v −(ŝ n ) v ] 2 where M is the cumulative metric, ŷ n represents a sample at the output of the feedforward equalizer, ŝ n is a noise-free signal component of ŷ n , where 0<v≤1.

4. The receiver of claim 3 , where v is given by

v
≈

1
+

0.5
⁢

log
⁡

(

M

2
,
1

/

M

2
,
0

)

log
⁡

(

S
0

/

S
1

)

,

where M 2,0 and M 2,1 are conditional second-order central moments of noise and where S 0 =f(0,0, . . . ,0), S 1 =f(1,1, . . . ,1).

5. The receiver of claim 3 further comprising:
a transformation block to provide an approximate solution to (ŷ n ) v , wherein the transformation block implements a function LUT(ŷ n )=(ŷ n +y min ) v when the sample ŷ n is in an interval between −y min and +y max , where y min and y max are the minimum and maximum values of the interval of the sample ŷ n , respectively.

6. A receiver comprising:
an analog-to-digital converter (ADC) that generates signal samples from a received signal having combined non-Gaussian noise and Gaussian noise;
wherein the ADC is a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
a 1-bit comparator coupled to the input track-and-hold stage,
a 1-bit digital-to-analog converter (DAC) coupled to the 1-bit comparator,
an analog subtractor coupled to the 1-bit DAC and the input track-and-hold stage,
a residue amplifier coupled to the analog subtractor, and
a track-and-hold circuit coupled to the residue amplifier;

a feedforward equalizer coupled to receive the signal samples from the ADC, and to apply equalization to generate equalized samples;
a decoder coupled to an output of the feedforward equalizer, the decoder determining detected symbols from the equalized samples and a channel model by minimizing a cumulative metric that compensates the combined Gaussian and non-Gaussian noise in the received signal; and
a channel estimator to receive the output of the feedforward equalizer and an output of the decoder and to generate the channel model and an error feedback signal to adaptively update coefficients of the feedforward equalizer based on the error feedback signal;
wherein the ADC further includes a look-up table (LUT) configured to the plurality of ADC stages to store the inverses of non-linear characteristics of the signal samples.

7. A receiver comprising:
an analog-to-digital converter (ADC) that generates signal samples from a received signal having combined non-Gaussian noise and Gaussian noise;
wherein the ADC is a pipelined ADC including an input track-and-hold stage followed by a plurality of low resolution ADC stages, each ADC stage including
a 1-bit comparator coupled to the input track-and-hold stage,
a 1-bit digital-to-analog converter (DAC) coupled to the 1-bit comparator,
an analog subtractor coupled to the 1-bit DAC and the input track-and-hold stage,
a residue amplifier coupled to the analog subtractor, and
a track-and-hold circuit coupled to the residue amplifier;

a feedforward equalizer coupled to receive the signal samples from the ADC, and to apply equa

Assignees

• Inphi Corp

Inventors

• Agazzi Oscar Ernesto
• Crivelli Diego Ernesto
• Carrer Hugo Santiago
• Hueda Mario Rafael
• Luna German Cesar Augusto
• Grace Carl

Classifications

• H04L25/03038

  with a non-recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L2025/03617

  Time recursive algorithms (H04L2025/03643 takes precedence) · CPC title

• H04L2025/03477

  not time-recursive · CPC title

• H04B2001/0441

  with linearisation using feed-forward · CPC title

• H04B10/5059 Primary

  using a feed-forward signal generated by analysing the optical or electrical input · CPC title