Lane-striped computation of packet CRC to maintain burst error properties

Patent metadata

Field	Value
Publication number	US-10097203-B2
Application number	US-201514939813-A
Country	US
Kind code	B2
Filing date	Nov 12, 2015
Priority date	Nov 12, 2015
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A CRC generator, a method for computing a CRC of a data packet, and an electronic system, such as a circuit board, are disclosed herein. In one embodiment the method is for computing the CRC of a data packet to be transmitted on a serial communications link having multiple lanes. In one embodiment, the CRC generator includes: (1) a CRC calculator configured to define a CRC calculation of a data packet in sequential order and perform parallelized computations, according to the sequential order and the multiple lanes, to generate sub-CRC values and (2) combination circuitry configured to combine the sub-CRC values to provide the CRC value for the packet.

First claim

What is claimed is:

1. A cyclic redundancy check (CRC) generator of a serial communications link having multiple lanes, comprising:
a CRC calculator configured to define a CRC calculation of a data packet, for transmission on said multiple lanes, in sequential order and to perform parallelized computations on each lane of said multiple lanes based on said sequential order to generate sub-CRC values; and
combination circuitry configured to combine said sub-CRC values to provide a final packet CRC value for said packet that maintains sequential error detection for said packet over said transmission on said multiple lanes.

2. The CRC generator as recited in claim 1 wherein said CRC calculator is configured to define said CRC calculation in sequential order according to a symbol number and a flit number.

3. The CRC generator as recited in claim 1 wherein said CRC calculator is configured to perform said parallelized computations in real time.

4. The CRC generator as recited in claim 1 wherein said parallelized computations includes initializing all but one of said sub-CRC values calculations with leading zeros.

5. The CRC generator as recited in claim 1 wherein said parallelized computations employs a fixed value for leading zero initialization.

6. The CRC generator as recited in claim 4 wherein said CRC calculator is further configured to adjust each of said sub-CRC values for trailing zeros.

7. The CRC generator as recited in claim 1 wherein said combination circuitry is XOR logic circuitry.

8. A method for transmitting a data packet on a serial communications link having multiple lanes, comprising:
defining a calculation for a cyclic redundancy check (CRC) value of a data packet in sequential order;
calculating, in parallel, a sub-CRC value of said CRC value for each lane of said multiple lanes; and
generating said CRC value for said data packet based on a combination of each said sub-CRC value, wherein said CRC value maintains sequential error detection for transmitting said data packet on said multiple lanes.

9. The method as recited in claim 8 wherein said calculating and said combining are performed in real time.

10. The method as recited in claim 8 further comprising employing leading zeros for calculating some of said sub-CRC values.

11. The method as recited in claim 8 wherein said calculating includes using a fixed value for leading zeros that is predetermined based on a maximum size of said data packet and a lane number.

12. The method as recited in claim 8 further comprising adjusting each said sub-CRC value for trailing zeros.

13. The method as recited in claim 12 wherein said adjusting includes employing a precomputed value for said trailing zeros.

14. The method as recited in claim 8 wherein at least part of said calculating is performed by linear feedback shift registers.

15. A circuit board, comprising:
a first device;
a second device; and
a serial communications link having multiple lanes communicatively coupling said first device to said second device, said serial communications link including a transmitter having a cyclic redundancy check (CRC) generator comprising:
a CRC calculator configured to define, in sequential order, a CRC of a data packet to transmit over said multiple lanes and to perform parallelized computations on each of said multiple lanes based on said sequential order to generate sub-CRC values; and
combination circuitry configured to combine said sub-CRC values to provide a final packet CRC value for said data packet that maintains sequential error detection for said data packet in transmissions over said serial communications link.

16. The circuit board as recited in claim 15 wherein said CRC calculator is configured to define said CRC in sequential order according to a symbol number and a flit number.

17. The circuit board as recited in claim 15 wherein said CRC calculator is configured to perform said parallelized computations in real time.

18. The circuit board as recited in claim 15 wherein said parallelized computations include initializing some of said sub-CRC value calculations with leading zeros.

19. The circuit board as recited in claim 18 wherein a fixed value is used for said leading zero initializations.

20. The circuit board as recited in claim 15 wherein said CRC calculator is further configured to adjust each of said sub-CRCs for trailing zeros.

Assignees

• Nvidia Corp

Inventors

• Tyson Eric
• Glaser Stephen D
• Osborn Mike
• Hummel Mark

Classifications

• H04L1/0061

  Error detection codes · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• H03M13/091 Primary

  Parallel or block-wise CRC computation · CPC title