Resynchronization of sample rate converters

Patent metadata

Field	Value
Publication number	US-10097200-B1
Application number	US-201715593981-A
Country	US
Kind code	B1
Filing date	May 12, 2017
Priority date	May 12, 2017
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A device having a sample-rate converter that may be programmed to generate samples at different rates is synchronized to an external synchronization pulse by temporarily changing the sample rate to a temporary sample rate and then changing the sample rate back to the original sample rate. Synchronization in a reduced amount of time is achieved by determining the interval between the synchronization pulse and one of the output samples and determining a processing time of the device for generating the output samples at a new rate. The system calculates a temporary sample rate based on these calculations that tends to reduce an amount of time to achieve synchronization.

First claim

The invention claimed is:

1. A method for synchronizing output samples of a device, including a programmable decimator, to a synchronization pulse, the method comprising:
determining an interval between the synchronization pulse and a pulse of a signal indicating that output samples of the device are ready, the signal indicating that the output samples of the device are ready having a specified rate;
in response to the interval, applying a temporary decimation factor to the programmable decimator to achieve a temporary output data rate, using the determined interval and a processing time of the device, to generate the output samples; and
after a specified delay, applying a decimation factor to the programmable decimator to provide output samples at the specified rate.

2. The method of claim 1 , further comprising determining the processing time and the interval based at least in part on one or more characteristics of the device.

3. The method of claim 2 wherein the device includes a sigma-delta modulator circuit having a filter and wherein the processing time includes a group delay of the filter.

4. The method of claim 3 , wherein the filter includes an N th order sinc filter, where N is an integer, and wherein the specified delay includes N periods of the of the signal indicating that the output samples of the device are ready.

5. The method of claim 3 , wherein the sigma-delta modulator is part of a sigma-delta analog-to-digital converter (ADC) circuit and the processing time includes a sum of the group delay of the filter and a calibration delay of the ADC and the filter.

6. The method of claim 3 , further comprising:
determining that the interval between the synchronization pulse and the signal indicating that output samples of the device are ready is less than or equal to one-half of the group delay of the filter and, in response to the determination, applying the decimation factor to the programmable decimator includes applying the decimation factor such that the temporary output data rate is greater than the specified rate.

7. The method of claim 3 , further comprising:
determining that the interval between the synchronization pulse and the signal indicating that output samples of the device are ready is greater than one-half of the group delay of the filter and, in response to the determination, applying the decimation factor to the programmable decimator includes applying the decimation factor such that the temporary output data rate is less than the specified rate.

8. The method of claim 1 wherein determining the interval between the synchronization pulse and the pulse of the signal indicating that output samples of the device are ready includes:
counting pulses of an input clock signal by a counter generate a count output signal;
receiving the count output signal as a first count value and resetting the counter responsive to a leading edge of the pulse of the signal indicating that output samples of the device are ready;
receiving the count output signal as a second count value and resetting the counter responsive to a leading edge of the synchronization pulse; and
responsive to the second count value indicating a time less than one half of a period of the signal indicating that output samples of the device are ready, determining the interval based on the second count value.

9. The method of claim 1 wherein determining the interval between the synchronization pulse and the pulse of the signal indicating that output samples of the device are ready includes:
counting pulses of an input clock signal by a counter to generate a count output signal;
receiving the count output signal as a first count value and resetting the counter responsive to a leading edge of the pulse of the signal indicating that output samples of the device are ready;
receiving the count output signal as a second count value and resetting the counter responsive to a leading edge of the synchronization pulse; and
responsive to the second count value indicating a time greater than one half of a period of the signal indicating that output samples of the device are ready, determining the interval based on the first count value.

10. An apparatus for synchronizing output samples of a device having a programmable decimator to a synchronization pulse, the apparatus comprising:
circuitry configured to determine an interval between the synchronization pulse and a pulse of a signal indicating that output samples of the device are ready, the signal indicating that the output samples of the device are ready having a specified rate; and
control circuitry configured to:
apply a temporary decimation factor to the programmable decimator to achieve a temporary output data rate, wherein the temporary decimation factor is based on the determined interval and on a processing time of the device to generate the output samples; and
after a specified delay, apply a decimation factor to the programmable decimator to change the output data rate to the specified rate.

11. The apparatus of claim 10 wherein the processing time is determined based at least in part on one or more characteristics of the device.

12. The apparatus of claim 11 , wherein the device includes a sigma-delta modulator circuit having a filter and the processing time includes a group delay of the filter.

13. The apparatus of claim 12 , wherein the filter is an Nth order-sine filter, where N is an integer, and wherein the specified delay includes N periods of the signal indicating that the output samples of the device are ready.

14. The apparatus of claim 12 , wherein device includes a sigma-delta. analog-to-digital converter (ADC) including the sigma-delta modulator, and the processing time is a sum of the group delay of the filter and a calibration delay of the ADC and the filter.

15. The apparatus of claim 12 , wherein the control circuitry is configured to apply the decimation factor such that the temporal) , output data rate is greater than the specified rate when the interval between the synchronization pulse and the signal indicating that output samples of the device are ready is less than or equal to one-half of the group delay of the filter.

16. The apparatus of claim 10 , wherein the control circuitry is configured to apply the decimation factor such that the temporary output data rate is less than the specified rate when the interval between the synchronization pulse and the signal indicating that output samples of the device are ready is greater than one-half of the group delay of the filter.

17. The apparatus of claim 10 further comprising:
a clock generator for generating an input clock signal for the programmable decimator; and
timer circuitry including a counter configured to count clock pulses of the input clock signal to provide a count output signal, wherein the timer circuitry is configured to:
receive the count output signal, the synchronization pulse, and the pulse of a signal indicating that output samples of the device are ready;
store the count output signal as a first count value and reset the counter, responsive to the pulse of the signal indicating that output samples of the device are ready; and
store the count output signal as a second count value and reset the counter, responsive to the synchronization pulse;

wherein the apparatus includes circuitry configured to determine the interval based on the second count value when the second count value indicates a time less than one half of a period of the signal indicating that output samples of the device are ready.

18. The apparatus

Assignees

• Analog Devices Global

Inventors

• Usach Merino Miguel
• Hennessy Michael
• O'Shaughnessy Anthony Evan
• Croke Claire

Classifications

• H04B14/046

  Systems or methods for reducing noise or bandwidth · CPC title

• H03M3/462 Primary

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M3/496

  Details of sampling arrangements or methods · CPC title

• H03M3/384

  Offset correction (removal of offset already present on the analogue input signal H03M3/494) · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title