Digital to analog converter with remote cascode devices

Patent metadata

Field	Value
Publication number	US-10097199-B1
Application number	US-201815893895-A
Country	US
Kind code	B1
Filing date	Feb 12, 2018
Priority date	Feb 12, 2018
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A digital to analog converter (DAC) circuit is disclosed which employs isolation providing cascode devices to reduce data dependent signal distortion. A DAC circuit configured according to an embodiment includes a current source associated with each bit of a digital word that is to be converted. Each current source is coupled to a current switch that is controlled by the associated bit. The DAC also includes a cascode device coupled to each of the current switches through a feed line. The DAC further includes a summing junction configured to generate an analog output signal corresponding to the digital word based on a sum of currents provided by the current sources, through the current switches and the feed lines. The cascode devices provide impedance matching and isolation between the feed lines and the summing junction to reduce signal reflections between the current switches and the summing junction to improve conversion performance.

First claim

What is claimed is:

1. A digital to analog converter (DAC) circuit comprising:
a plurality of current switches, each of the current switches controlled by a selected bit of a digital word;
a plurality of cascode devices, each cascode device coupled to one of the current switches through a feed line;
a summing junction to generate an analog output signal corresponding to the digital word, based on a sum of currents provided by current source devices, through the current switches and the feed lines, wherein the cascode devices provide isolation between the feed lines and the summing junction; and
a resistor coupled in series between the cascode device and the feed line coupled to the cascode device, the resistor selected to match a characteristic impedance of the feed line to an input impedance of the cascode device.

2. The DAC circuit of claim 1 , wherein the feed lines, the cascode devices, and the summing junction are configured in a differential topology.

3. The DAC circuit of claim 1 , wherein the current source devices are complementary metal oxide semiconductor field effect transistors.

4. The DAC circuit of claim 1 , further comprising a code word generation circuit to generate the bits of the digital word for control of the current switches.

5. The DAC circuit of claim 1 , wherein the current switches, feed lines, cascode devices, and summing junction are disposed on an integrated circuit, and the distance between the current switches and the cascode devices is greater than the distance between the cascode devices and the summing junction.

6. The DAC circuit of claim 1 , wherein the distance between the current switches and the cascode devices is greater than the distance between any one of the cascode devices and any other of the cascode devices.

7. A communications system comprising:
a digital to analog converter (DAC) circuit including
a plurality of current switches, each of the current switches controlled by a selected bit of a digital word,
a plurality of cascode devices, each cascode device coupled to one of the current switches through a feed line, and
a summing junction to generate an analog output signal corresponding to the digital word, based on a sum of currents provided by current source devices, through the current switches and the feed lines, wherein the cascode devices provide isolation between the feed lines and the summing junction;

a code word generation circuit to generate the bits of the digital word for control of the current switches; and
a transmitter circuit to convert the analog output signal to a selected radio frequency for transmission through an antenna.

8. The communications system of claim 7 , wherein an input impedance of the cascode device matches a characteristic impedance of the feed line coupled to the cascode device, the input impedance based on a transconductance of the cascode device, the transconductance associated with dimensions of the cascode device.

9. The communications system of claim 7 , wherein an input impedance of the cascode device matches a characteristic impedance of the feed line coupled to the cascode device, based on application of a bias current to the cascode device.

10. The communications system of claim 7 , wherein the DAC circuit further comprises a resistor coupled in series between the cascode device and the feed line coupled to the cascode device, the resistor selected to match a characteristic impedance of the feed line to an input impedance of the cascode device.

11. The communications system of claim 7 , wherein dimensions of the feed line are selected to match a characteristic impedance of the feed line to an input impedance of the cascode device coupled to the feed line.

12. A method for fabricating a digital to analog converter, the method comprising:
configuring a plurality of current switches to be controlled by a selected bit of a digital word;
coupling each of a plurality of cascode devices to one of the current switches through a feed line;
providing a summing junction to generate an analog output signal corresponding to the digital word, based on a sum of currents provided by current source devices, through the current switches and the feed lines;
coupling the summing junction to the feed lines through the cascode devices, wherein the cascode devices provide isolation between the feed lines and the summing junction; and
configuring an input impedance of the cascode device to match a characteristic impedance of the feed line coupled to the cascode device, the input impedance based on a transconductance of the cascode device, the transconductance associated with dimensions of the cascode device.

13. The method of claim 12 , further comprising coupling a resistor in series between the cascode device and the feed line coupled to the cascode device, the resistor selected to match a characteristic impedance of the feed line to an input impedance of the cascode device.

Assignees

• Bae Sys Inf & Elect Sys Integ

Inventors

• Kushner Lawrence J
• Stuenkel Mark E
• Turner Steven E

Classifications

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03M1/742 Primary

  using current sources as quantisation value generators · CPC title

• G06F9/223

  Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems · CPC title