Wide capture range reference-less frequency detector

Patent metadata

Field	Value
Publication number	US-10097190-B2
Application number	US-201615394506-A
Country	US
Kind code	B2
Filing date	Dec 29, 2016
Priority date	Dec 19, 2016
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.

First claim

What is claimed is:

1. A reference-less frequency detector circuit, comprising:
a sampling circuit configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate, the frequency control voltage comprising a frequency down indication and a frequency up indication; and
a voltage-to-current converter circuit coupled to the sampling circuit and configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal, the voltage-to-current converter circuit comprising an output switching circuit controlled by the switch control signal and configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication,
wherein the output switching circuit comprises first and second transistors coupled in series with each other and having a complementary type with each other, wherein an output node for the output switching circuit is a common node between the first and second transistors.

2. The circuit of claim 1 , wherein the output switching circuit further comprises:
a first series circuit comprising the first and second transistors, a gate of the first transistor coupled to the output of the sampling circuit, and a gate of the second transistor coupled to an inverse of the output of the sampling circuit;
a second series circuit comprising third and fourth transistors coupled in series with each other and having a complementary type with each other, a gate of the third transistor coupled to the inverse of the output of the sampling circuit, and a gate of the fourth transistor coupled to the output of the sampling circuit, wherein the first and second series circuits are coupled together in parallel at first and second common nodes;
a fifth transistor coupled between a supply node and the first common node;
a sixth transistor coupled between a circuit reference node and the second common node; and
a voltage divider network coupled between the supply node and the circuit reference node, the voltage divider network configured to provide a voltage to a common node between the third and fourth transistors.

3. The circuit of claim 2 , wherein the circuit reference node is circuit ground.

4. The circuit of claim 2 , wherein the first and third transistors are p-type field effect transistors (PFETs), and the second and fourth transistors are n-type field effect transistors (NFETs).

5. The circuit of claim 2 , wherein the voltage-to-current converter circuit further comprises:
a first pair of transistors coupled in series with each other and having a complementary type with each other, wherein a gate of one of the first pair of transistors is coupled to an output of a sampling circuit and configured to operate in response to a first state of the frequency control voltage;
a second pair of transistors coupled in series with each other and having a complementary type with each other, wherein a gate of one of the second pair of transistors is coupled to the output of the sampling circuit and configured to operate in response to a second state of the frequency control voltage, the second state being an inverse of the first state, wherein the first and second pair of transistors are coupled in parallel at a first common node and a second common node, the first common node coupled to the supply node; and
a current source coupled between the circuit reference node and the second common node.

6. The circuit of claim 5 , wherein remaining transistors of the first and second pairs of transistors are each coupled in a diode configuration and coupled to the supply node.

7. The circuit of claim 6 , wherein a gate of the fifth transistor is coupled to a gate of the remaining transistor of the second pair of transistors.

8. The circuit of claim 2 , wherein the substantially equal respective latencies for the frequency down indication and the frequency up indication are each based on a one transistor latency.

9. The circuit of claim 8 , wherein the one transistor latency for the frequency up indication comprises the first transistor and the one transistor latency for the frequency down indication comprises the second transistor.

10. A clock/data recovery system, comprising:
a voltage controlled oscillator configured to generate a clock signal;
a phase detector coupled to the voltage controlled oscillator and configured to generate a buffered data signal and a phase difference control signal based on an input data signal and the clock signal, wherein the phase difference control signal is indicative of a phase difference between the clock signal and the input data signal;
a reference-less frequency detector coupled to the voltage controlled oscillator and configured to generate a frequency difference control signal indicative of a frequency difference between the input data signal and the clock signal, the reference-less frequency detector comprising:
a sampling circuit configured to generate a frequency control voltage and a switch circuit control signal based on the frequency difference between the clock signal and the input data signal, the frequency control voltage comprising a frequency down indication and a frequency up indication; and
a voltage-to-current converter circuit coupled to the sampling circuit and configured to convert the frequency control voltage to a frequency control current in response to the switch circuit control signal, the voltage-to-current converter circuit comprising an output switch circuit controlled by the switch control signal and configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication; and

a filter coupled to the phase detector and the reference-less frequency detector and configured to output a control signal to the voltage controlled oscillator, wherein the control signal provides an indication of a phase difference and a frequency difference between the input data signal and the clock signal.

11. The system of claim 10 , further comprising a re-timer circuit coupled to the voltage controlled oscillator and the phase detector, the re-timer circuit configured to clock out the buffered data signal in response to the clock signal.

12. The system of claim 10 , wherein the switch circuit control signal is coupled to one transistor, having a first transistor latency, to generate the frequency up indication and one transistor, having a second transistor latency, to generate the frequency down indication, wherein the first and second transistor latencies are the same.

13. The system of claim 10 , wherein the sampling circuit comprises a first flip-flop, having a data input coupled to the clock signal and a clock input coupled to the delayed data signal, to generate the switch circuit control signal.

14. The system of claim 13 , wherein the sampling circuit further comprises a second flip-flop coupled in series with a third flip-flop, the second flip-flop having a data input coupled to the clock signal and a clock input coupled to the input data signal, the third flip-flop having a data input coupled to an output of the second flip-flop and a clock input coupled to an output of the first flip-flop.

15. A method for generating a frequency control signal from a reference-less frequency detector, the method comprising:
generating an up/down control voltage, wherein the up/down control voltage is indicative of a frequency difference between an input data rate and a clock signal frequency, and comprises an up frequency indication voltage o

Assignees

• Futurewei Technologies Inc

Inventors

• Gu Liang
• Cao Yuming
• Dang Yen
• Lei Gong
• Gu Yifan
• Lee Hung-Yi
• Deshpande Mamatha
• Shih Shou-Po
• Liu Miao

Classifications

• H03L7/0896

  the current generators being controlled by differential up-down pulses · CPC title

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title