Power amplifier time-delay invariant predistortion methods and apparatus

Patent metadata

Field	Value
Publication number	US-10097142-B2
Application number	US-201514788567-A
Country	US
Kind code	B2
Filing date	Jun 30, 2015
Priority date	May 1, 2002
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

An embodiment of the invention is a time-delay invariant predistortion approach to linearize power amplifiers in wireless RF transmitters. The predistortion architecture is based on the stored-compensation or memory-compensation principle by using a combined time-delay addressing method, and therefore, the architecture has an intrinsic, self-calibrating time-delay compensation function. The predistortion architecture only uses a lookup table to conduct both the correction of non-linear responses of a power amplifier and the compensation of any time-delay effects presented in the same system. Due to the time-delay invariant characteristic, the predistortion design has a wider dynamic range processing advantage for wireless RF signals, and therefore can be implemented in multi-carrier and multi-channel wireless systems.

First claim

What is claimed is:

1. A predistortion system for linearizing the output of a power amplifier, the predistortion system comprising:
a first receiver configured to receive a first signal representative of a radio frequency (RF) modulated signal;
a second receiver configured to receive a feedback signal representative of at least one nonlinear characteristic of the power amplifier; and
a predistortion controller communicatively coupled with both the first receiver and the second receiver, wherein the predistortion controller comprises at least one lookup table of a predetermined size, and wherein an output of the lookup table includes a time delay correction element.

2. The predistortion system of claim 1 wherein the inputs are further derived from a difference between the square of a quadrature component of the first signal and the square of a quadrature component of the feedback signal.

3. The predistortion system of claim 1 wherein the inputs are further derived from a difference between the square of an in-phase component of the first signal and the square of an in-phase component of the feedback signal.

4. The predistortion system of claim 1 , further comprising a reference path communicatively coupled with the first receiver and the predistortion controller.

5. The predistortion system of claim 4 , further comprising a feedback path communicatively coupled with the second receiver and the predistortion controller.

6. The predistortion system of claim 5 wherein the at least one lookup table is configured to store at least one time-delay value that compensates for a time delay between the reference path and the feedback path.

7. The predistortion system of claim 6 wherein the at least one lookup table is further configured to adaptively update at least one correction value in the lookup table by combining a non-linear correction value of the power amplifier with the at least one time-delay value.

8. The predistortion system of claim 1 wherein the predistortion controller is configured to generate a correction factor for correcting at least one nonlinear characteristic of the power amplifier based on at least an input of the lookup table.

9. The predistortion system of claim 8 , further comprising a processor configured to combine the RF modulated signal with a second signal corresponding to the correction factor.

10. The predistortion system of claim 9 wherein the processor is further configured to supply the combined RF modulated signal with the feedback signal to the power amplifier to linearize the output of the power amplifier.

11. The predistortion system of claim 8 , further comprising combining logic to combine the RF modulated signal with a signal corresponding to the correction factor.

12. The predistortion system of claim 11 wherein combining logic is performed to also supply the combined RF modulated signal and feedback signal to the power amplifier to linearize the output of the power amplifier.

13. The predistortion system of claim 1 , further comprising a serial shift register for forming an address for the lookup table.

14. The predistortion system of claim 1 wherein the lookup table is addressed by parallel signals.

15. The predistortion system of claim 1 wherein the feedback signal is an analog signal.

16. The predistortion system of claim 15 , further comprising a digital-to-analog converter.

17. The predistortion system of claim 16 wherein the digital-to-analog converter is configured to convert a digital signal corresponding to a correction factor of the feedback signal.

18. The predistortion system of claim 1 wherein the lookup table comprises at least one correction value.

19. The predistortion system of claim 18 wherein the at least one correction value falls within a range determined by the predetermined size of the lookup table.

20. The predistortion system of claim 1 wherein the lookup table is configured to respond to inputs derived from outputs of the at least one lookup table.

Assignees

• Dali Wireless Inc

Inventors

• Yang Dali
• Yang Jia

Classifications

• H04B2001/0425

  with linearisation using predistortion · CPC title

• H03F2201/3224

  Predistortion being done for compensating memory effects · CPC title

• H04L1/0044

  specially adapted for power saving · CPC title

• H03F1/3241

  using predistortion circuits (H03F1/3211, H03F1/3217 take precedence) · CPC title

• H04B1/0475

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title