Doherty input power splitter and linearization method

US10097138B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10097138-B2
Application numberUS-201615353791-A
CountryUS
Kind codeB2
Filing dateNov 17, 2016
Priority dateJul 26, 2016
Publication dateOct 9, 2018
Grant dateOct 9, 2018

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Embodiments of a Doherty amplifier device are provided, including a first amplifier stage having a first gain; a second amplifier stage having a second gain that is less than the first gain; and an input power splitter coupled to inputs of the first and second amplifier stages, wherein the input power splitter includes either an inductive element, a capacitive element, or both coupled between the inputs of the first and second amplifier stages, and a resistive element coupled to the input of the second amplifier stage, the input power splitter respectively delivers first and second power levels to inputs of the first and second amplifier stages, and the resistive element is configured to tune gain linearity of the Doherty amplifier device by increasing the second power level to be greater than the first power level, based on a ratio of the second gain to the first gain.

First claim

Opening claim text (preview).

What is claimed is: 1. A Doherty amplifier device comprising: a first amplifier stage having a first gain; a second amplifier stage having a second gain that is less than the first gain; and an input power splitter coupled to an input of the first amplifier stage and coupled to an input of the second amplifier stage, wherein the input power splitter comprises either an inductive element, a capacitive element, or both coupled in series between the inputs of the first and second amplifier stages, and a resistive element coupled between the input of the second amplifier stage and ground, the input power splitter is configured to deliver a first power level to the input of the first amplifier stage and a second power level to the input of the second amplifier stage, and the resistive element is configured to tune gain linearity of the Doherty amplifier device by increasing the second power level to be greater than the first power level, based at least in part on a ratio of the second gain to the first gain. 2. The device of claim 1 , wherein the resistive element comprises a resistor having a resistive value selected for optimal gain linearity of the Doherty amplifier device, based at least in part on one or more operating parameters of the Doherty amplifier device that include: the ratio of the second gain to the first gain, a frequency of a presently received input signal, an envelope amplitude of the presently received input signal, and an operating power level of the Doherty amplifier device. 3. The device of claim 2 , wherein the resistive element is connected to the input of the second amplifier stage by an external terminal located on a carrier substrate and the resistor is selected from one of a number of resistors having different resistive values configured to dynamically tune the gain linearity of the Doherty amplifier for different operating parameters. 4. The device of claim 2 , wherein the resistive element further comprises a capacitive element and an inductive element connected either in parallel or in series, and the resistor is connected to at least the inductive element via an external terminal located on a carrier substrate. 5. The device of claim 4 , wherein a capacitive value of the capacitive element and an inductance value of the inductive element are controllable. 6. The device of claim 2 , wherein the resistive element comprises a variable capacitor having an adjustable capacitive value that is controllable by an external control voltage, based on the frequency of the presently received input signal. 7. The device of claim 1 , further comprising: a controller coupled to the resistive element, wherein the resistive element comprises a variable resistor having an adjustable resistive value, and the controller is configured to control the adjustable resistive value to an optimal resistive value for the Doherty amplifier device, based at least in part on the ratio of the second gain to the first gain. 8. The device of claim 7 , wherein the controller comprises a look-up table, the look-up table comprises a plurality of parameter sets, each parameter set associated with one of a plurality of resistive values, each parameter set includes one or more operating parameters of the Doherty amplifier device, the controller is configured to look up a present parameter set in the look-up table to select the optimal resistive value for the adjustable resistive value of the variable resistor. 9. The device of claim 8 , wherein the present parameter set includes one or more of: the ratio of the second gain to the first gain, a frequency of a presently received input signal, an envelope amplitude of the presently received input signal, and an operating power level of the Doherty amplifier device, and the controller is configured to look up the present parameter set in response to a change of any operating parameter included in the present parameter set. 10. The device of claim 1 , further comprising: a first pre-matching network and a second pre-matching network respectively coupled between the inputs of the first and second amplifier stages and the input power splitter, wherein the first and second amplifier stages and the first and second pre-matching networks are integrated on a semiconductor die attached to a carrier substrate, and the input power splitter is located off of the semiconductor die. 11. An electronic circuit comprising a Doherty amplifier device, the electronic circuit comprises: an input power splitter having a first node coupled to an input of a main amplifier stage and a second node coupled to an input of a peak amplifier stage, the input power splitter configured to: provide a first signal having a first power level to the input of the main amplifier stage, and provide a second signal having a second power level to the peak amplifier stage, wherein the main amplifier stage has a first gain, the peak amplifier stage has a second gain that is less than the first gain, and the input power splitter comprises either an inductive element, a capacitive element, or both coupled in series between the first and second nodes, and a resistive element coupled between the second node and ground, wherein the resistive element is configured to adjust the second power level to be greater than the first power level in order to tune gain linearity of the Doherty amplifier device, based at least in part on a ratio of the second gain to the first gain. 12. The circuit of claim 11 , further comprising: a first pre-matching network coupled between the input power splitter and the input of the main amplifier stage, and a second pre-matching network coupled between the input power splitter and the input of the peak amplifier stage, wherein each of the first and second pre-matching networks comprise a first capacitance coupled in series with a first inductance between the input power splitter and the respective input of the main and peak amplifier stages, and a second inductance coupled in series with a second capacitance between the respective input of the main and peak amplifier stages and ground. 13. The circuit of claim 12 , wherein the main and peak amplifier stages and the first and second pre-matching networks are integrated on a semiconductor die attached to a carrier substrate, and the input power splitter is located off of the semiconductor die. 14. The circuit of claim 11 , wherein the resistive element comprises one resistor selected from a plurality of resistors having a plurality of resistive values configured to dynamically tune the gain linearity of the Doherty amplifier device for different operating parameters, the one resistor selected based on a combination of present operating parameters of the Doherty amplifier device that include one or more of: the ratio of the second gain to the first gain, a frequency of a presently received input signal, an envelope amplitude of the presently received input signal, and an operating power level of the Doherty amplifier device. 15. The circuit of claim 14 , wherein the resistive element further comprises a capacitive element and an inductive element connected either in parallel or in series, the one resistor is connected to at least the inductive element, and a capacitance value of the capacitive element and an inductance value of the inductive element are controllable. 16. The circuit of claim 11 , wherein the resistive element comprises a voltage-controlled variable capacitive element having an adjustable capacitive value based on a frequency of a presently received input signal, the adjustable capac

Assignees

Inventors

Classifications

  • An input signal being distributed in parallel over the inputs of a plurality of power amplifiers · CPC title

  • H03F1/0288Primary

    using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers · CPC title

  • in integrated circuits · CPC title

  • An impedance adaptation circuit being added at the input of a power amplifier stage · CPC title

  • using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

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What does patent US10097138B2 cover?
Embodiments of a Doherty amplifier device are provided, including a first amplifier stage having a first gain; a second amplifier stage having a second gain that is less than the first gain; and an input power splitter coupled to inputs of the first and second amplifier stages, wherein the input power splitter includes either an inductive element, a capacitive element, or both coupled between t…
Who is the assignee on this patent?
Nxp Usa Inc
What technology area does this patent fall under?
Primary CPC classification H03F1/0288. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 09 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).