Radiation detector comprising a compensating sensor

Patent metadata

Field	Value
Publication number	US-10096724-B2
Application number	US-201514951554-A
Country	US
Kind code	B2
Filing date	Nov 25, 2015
Priority date	Nov 25, 2014
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A chip for radiation measurements, the chip comprising a first substrate comprising a first sensor and a second sensor. The chip moreover comprises a second substrate comprising a first cavity and a second cavity both with oblique walls. An internal layer is present on the inside of the second cavity. The second substrate is sealed to the first substrate with the cavities on the inside such that the first cavity is above the first sensor and the second cavity is above the second sensor.

First claim

The invention claimed is:

1. A chip for radiation measurements, the chip comprising
a first substrate comprising at least a first sensor and a second sensor,
a second substrate comprising at least a first cavity and a second cavity both with oblique walls,
wherein an internal layer is present on the inside of the second cavity, the internal layer being configured to attenuate incoming radiation by more than 10 dB before it reaches the second sensor, and
wherein the second substrate is sealed to the first substrate with the cavities on the inside such that the first cavity is above the first sensor and the second cavity is above the second sensor.

2. A chip according to claim 1 , wherein the internal layer is a reflective layer.

3. A chip according to claim 1 , wherein the internal layer is an absorption layer.

4. A chip according to claim 1 wherein the height of the second cavity is smaller than the height of the first cavity.

5. A chip according to claim 1 wherein a barrier is present between the first cavity and the second cavity and wherein the internal layer is present on the inside of the second cavity and at least partly on the barrier.

6. A chip according to claim 5 , wherein the barrier is sealed to the first substrate.

7. A chip according to claim 5 , wherein a channel is present between the barrier and the first substrate extending from the first cavity towards the second cavity.

8. A chip according to claim 5 , wherein the barrier is partially sealed to the first substrate leaving a channel between the barrier and the first substrate whereby the channel extends from the first cavity to the second cavity.

9. A chip according to claim 1 , wherein the internal layer also partly covers the inside of the first cavity.

10. A chip according to claim 1 , wherein the first sensor and/or the second sensor are thermopile sensors.

11. A chip according to claim 1 , wherein the internal layer is provided at least at the top wall of the second cavity and that the internal layer also covers at least the side wall of the first cavity facing the second cavity.

12. A chip comprising:
a first substrate that includes a first sensor and a second sensor
wherein the first sensor is configured to sense incoming radiation and the second sensor is a reference sensor; and

a second substrate coupled to the first substrate, the second substrate defining a first cavity and a second cavity;
wherein the first cavity is arranged above the first sensor, the first cavity being defined at least by first sidewalls, the first sidewalls including first oblique sidewalls;
wherein the second cavity is arranged above the second sensor, the second cavity being defined at least by second sidewalls, the second sidewalls including second oblique sidewalls;

wherein the chip further includes an internal layer arranged on an inside portion of the second cavity, and
the internal layer is configured to attenuate incoming radiation by more than 10 dB before it reaches the second sensor.

13. The chip according to claim 12 , wherein the internal layer arranged on the inside of the second cavity is arranged on at least a portion of the second oblique sidewalls.

14. A chip according to claim 12 , wherein the internal layer is provided at least at a top wall defining the second cavity, the top wall of the second cavity directly opposing the second sensor.

15. A chip according to claim 12 , wherein the internal layer covers at least a portion of the first sidewalls of the first cavity, the portion of the first sidewalls of the first cavity covered by the internal layer being a portion of the first sidewalls being closest to the second cavity.

16. A chip according to claim 12 , wherein the internal layer partly covers at least a portion of an inside surface of the first cavity.

Assignees

• Melexis Technologies Nv

Inventors

• Van Buggenhout Carl
• Van Der Wiel Appolonius Jacobus
• Buydens Luc

Classifications

• G01J1/0295

  Constructional arrangements for removing other types of optical noise or for performing calibration · CPC title

• H01L27/1443

  Electricity · mapped topic

• H01L35/34

  Electricity · mapped topic

• G01J5/045

  Sealings; Vacuum enclosures; Encapsulated packages; Wafer bonding structures; Getter arrangements (getter arrangements per se H10W76/48, H10P36/03) · CPC title

• G01J5/12

  using thermoelectric elements, e.g. thermocouples · CPC title