Power module package

Patent metadata

Field	Value
Publication number	US-10096562-B2
Application number	US-201615209777-A
Country	US
Kind code	B2
Filing date	Jul 14, 2016
Priority date	Jul 22, 2015
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A power module package includes a single-layered circuit board, a first electronic component, and a second electronic component. The single-layered circuit board includes an insulating substrate and a conductive layer thereon. A bottom surface of the conductive layer touches a top surface of the insulating substrate. The insulating substrate has plural first openings to allow the conductive layer to be exposed from the bottom surface of the insulating substrate. The first electronic component is disposed on a top surface of the conductive layer. The second electronic component is disposed on the bottom surface of the insulating substrate and received in the first openings. The second electronic component is connected to the conductive layer via the first openings. At least one of the first electronic component and the second electronic component is a bare die.

First claim

What is claimed is:

1. A power module package comprising:
a single-layered circuit board comprising an insulating substrate and a conductive layer disposed on the insulating substrate, the insulating substrate having a top surface and a bottom surface opposite to each other, the conductive layer having a top surface and a bottom surface opposite to each other, wherein the bottom surface of the conductive layer touches the top surface of the insulating substrate, and the insulating substrate has a plurality of first openings to allow the bottom surface of the conductive layer to be exposed from the bottom surface of the insulating substrate;
a first electronic component disposed on the top surface of the conductive layer; and
a second electronic component disposed on the bottom surface of the insulating substrate and embedded in the first openings, wherein the second electronic component is connected to the conductive layer via the first openings, and at least one of the first electronic component and the second electronic component is a bare die.

2. The power module package of claim 1 , wherein the bare die is a planar die, and the planar die is bonded to the conductive layer in a flip-chip bonding manner.

3. The power module package of claim 2 , further comprising a third electronic component, wherein the second electronic component is a capacitor, at least one of the first electronic component and the third electronic component is a planar die, and the third electronic component is disposed on the top surface of the conductive layer.

4. The power module package of claim 3 , further comprising two driving components respectively used for driving the first electronic component and the third electronic component, both the driving components being disposed in the first openings on the bottom surface of the insulating substrate, wherein orthogonal projections of the driving components onto the insulating substrate respectively overlap orthogonal projections of the first electronic component and the third electronic component onto the insulating substrate.

5. The power module package of claim 4 , wherein the first electronic component and the third electronic component are both gallium nitride dies, and orthogonal projections of the driving components onto the insulating substrate respectively overlap orthogonal projections of source electrodes and gate electrodes of the gallium nitride dies onto the insulating substrate.

6. The power module package of claim 2 , further comprising a third electronic component, a fourth electronic component, and a fifth electronic component, each of the first electronic component and the third electronic component being a low voltage metal-oxide-semiconductor transistor disposed on the top surface of the conductive layer, both the second electronic component and the fourth electronic component being gallium nitride dies disposed on the bottom surface of the insulating substrate, the fifth electronic component being a capacitor disposed on the top surface of the conductive layer, wherein the second electronic component and the fourth electronic component are connected to the conductive layer in the first openings, and orthogonal projections of the low voltage metal-oxide-semiconductor transistors onto the insulating substrate respectively overlap orthogonal projections of source electrodes of the gallium nitride dies corresponding to the low voltage metal-oxide-semiconductor transistors onto the insulating substrate.

7. The power module package of claim 6 , further comprising two driving components for respectively driving the low voltage metal-oxide-semiconductor transistors.

8. The power module package of claim 2 , wherein the first electronic component is a low voltage metal-oxide-semiconductor transistor, the second electronic component is a gallium nitride die, and an orthogonal projection of the low voltage metal-oxide-semiconductor transistor onto the insulating substrate overlaps an orthogonal projection of a source electrode of the gallium nitride die onto the insulating substrate.

9. The power module package of claim 1 , wherein the conductive layer has at least one concave portion, and the first electronic component is disposed in the concave portion.

10. The power module package of claim 1 , wherein the conductive layer is a copper layer.

11. The power module package of claim 1 , further comprising an encapsulating plastic completely or partially wrapping the single-layered circuit board and the first electronic component disposed on the single-layered circuit board.

12. The power module package of claim 11 , wherein a portion of the first electronic component is exposed from the encapsulating plastic, and the power module package further comprises a heat dissipation component disposed on the first electronic component.

13. The power module package of claim 12 , further comprising a heat conductive material disposed between the heat dissipation component and the first electronic component.

14. The power module package of claim 1 , wherein the insulating substrate comprises a plurality of second openings to expose the conductive layer, the power module package further comprises a plurality of connecting structures disposed in the second openings on the bottom surface of the insulating substrate and are connected to the conductive layer in the second openings, or the plurality of connecting structures are directly disposed on the top surface of the conductive layer.

15. The power module package of claim 14 , further comprising an isolation layer covering the bottom surface of the insulating substrate, the isolation layer having a plurality of third openings, each of the first openings and the second openings and the third opening corresponding to the each of the first openings and the second openings communicating with each other vertically.

16. The power module package of claim 14 , wherein the connecting structures are solder balls or pins.

17. The power module package of claim 1 , further comprising an insulating layer disposed on the conductive layer, the insulating layer comprising a plurality of fourth openings, wherein the first electronic component is connected to the conductive layer via the fourth openings.

18. The power module package of claim 1 , further comprising a isolation layer covering part of the top surface of the conductive layer.

Assignees

• Delta Electronics Inc

Inventors

• Liang Le
• Lu Kai
• Zhao zhen-qing
• Li Zeng

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H01L23/49838

  Electricity · mapped topic