Single crystal rhombohedral epitaxy of SiGe on sapphire at 450° C.-500° C. substrate temperatures

US10096472B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10096472-B2
Application numberUS-201615386592-A
CountryUS
Kind codeB2
Filing dateDec 21, 2016
Priority dateDec 21, 2015
Publication dateOct 9, 2018
Grant dateOct 9, 2018

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Abstract

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Various embodiments may provide a low temperature (i.e., less than 850° C.) method of Silicon-Germanium (SiGe) on sapphire (Al 2 O 3 ) (SiGe/sapphire) growth that may produce a single crystal film with less thermal loading effort to the substrate than conventional high temperature (i.e., temperatures above 850° C.) methods. The various embodiments may alleviate the thermal loading requirement of the substrate, which in conventional high temperature (i.e., temperatures above 850° C.) methods had surface temperatures within the range of 850° C.-900° C. The various embodiments may provide a new thermal loading requirement of the sapphire substrate for growing single crystal SiGe on the sapphire substrate in the range of about 450° C. to about 500° C.

First claim

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What is claimed is: 1. A method of growing a Silicon-Germanium (SiGe) layer on a sapphire (Al 2 O 3 ) wafer, comprising: providing a sapphire wafer; heating the sapphire wafer to a wafer surface temperature at or below about 500° C.; growing mono-crystalline SiGe on the sapphire wafer at the wafer surface temperature thereby forming a SiGe/sapphire wafer including a SiGe layer and an Al 2 O 3 substrate; and cooling the SiGe/sapphire wafer. 2. The method of claim 1 , wherein heating, growing, and cooling is completed in less than one hour. 3. The method of claim 2 , wherein the growing occurs immediately after the heating without a thermal soak step. 4. The method of claim 3 , wherein a separate silicon (Si) layer is not deposited on the sapphire wafer prior to the growing. 5. The method of claim 4 , wherein the wafer surface temperature is about 500° C. 6. The method of claim 4 , wherein the wafer surface temperature is about 450° C. 7. The method of claim 4 , wherein the wafer surface temperature is about 450° C. to about 500° C. 8. The method of claim 1 , wherein the wafer surface temperature is about 500° C. 9. The method of claim 1 , wherein the wafer surface temperature is about 450° C. 10. The method of claim 1 , wherein the wafer surface temperature is about 450° C. to about 500° C. 11. A semiconductor device, comprising: a Silicon-Germanium (SiGe) layer and a sapphire (Al 2 O 3 ) layer substrate, wherein the layers are formed by: providing a sapphire wafer; heating the sapphire wafer to a wafer surface temperature at or below about 500° C.; growing mono-crystalline SiGe on the sapphire wafer at the wafer surface temperature thereby forming a SiGe/sapphire wafer including a SiGe layer and an Al 2 O 2 substrate; and cooling the SiGe/sapphire wafer. 12. The semiconductor device of claim 11 , wherein heating, growing, and cooling is completed in less than one hour. 13. The semiconductor device of claim 12 , wherein the growing occurs immediately after the heating without a thermal soak step. 14. The semiconductor device of claim 13 , wherein a separate silicon (Si) layer is not deposited on the sapphire wafer prior to the growing. 15. The semiconductor device of claim 11 , wherein the wafer surface temperature is about 500° C. 16. The semiconductor device of claim 11 , wherein the wafer surface temperature is about 450° C. 17. The method of claim 11 , wherein the wafer surface temperature is about 450° C. to about 500° C. 18. The method of claim 14 , wherein the wafer surface temperature is about 500° C. 19. The method of claim 14 , wherein the wafer surface temperature is about 450° C. 20. The method of claim 14 , wherein the wafer surface temperature is about 450° C. to about 500° C.

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What does patent US10096472B2 cover?
Various embodiments may provide a low temperature (i.e., less than 850° C.) method of Silicon-Germanium (SiGe) on sapphire (Al 2 O 3 ) (SiGe/sapphire) growth that may produce a single crystal film with less thermal loading effort to the substrate than conventional high temperature (i.e., temperatures above 850° C.) methods. The various embodiments may alleviate the thermal loading requirement o…
Who is the assignee on this patent?
Nasa, Nasa
What technology area does this patent fall under?
Primary CPC classification H10P14/3411. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 09 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).