Memory array with flash and random access memory and method therefor, reading data from the flash memory without storing the data in the random access memory

Patent metadata

Field	Value
Publication number	US-10096350-B2
Application number	US-201213663099-A
Country	US
Kind code	B2
Filing date	Oct 29, 2012
Priority date	Mar 7, 2012
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

Memory array, system and method for storing data. The memory array has a flash memory array, a random access memory array coupled to the flash memory and configured to receive the data, a memory management module and a data bus. The memory management module is coupled to the random access memory array and to the flash memory array, the memory management module being configured to transfer at least a portion of the data stored in the random access memory array to the flash memory array. The data bus is coupled to the flash memory array and configured to output at least a portion of the data originally stored in the random access memory array from the flash memory array.

First claim

What is claimed is:

1. A memory array for storing data, comprising:
a flash memory array;
a random access memory array operatively coupled to said flash memory, said random access memory and said flash memory configured to receive said data;
a memory management module operatively coupled to said random access memory array and to said flash memory array, said memory management module being configured to transfer at least a portion of said data stored in said random access memory array to said flash memory array; and
a data bus operatively coupled to said flash memory array and configured to output directly said at least a portion of said data in said flash memory array without again storing said output in said random access memory array,
wherein said memory management module is configured to receive, from an external controller operatively coupled to said memory array and having firmware configured to control, at least in part, said memory array, an interrupt command generated in response to a detected operation of an implantable medical device.

2. The memory array of claim 1 wherein said random access memory array comprises a static random access memory array.

3. The memory array of claim 1 wherein said flash memory array comprises a plurality of sectors, at least one of said plurality of sectors having a data storage capacity and wherein said memory management module is configured to transfer said at least a portion of said data from said random access memory array to said flash memory array when said at least a portion of said data stored in said random access memory array equals said data storage capacity of said at least one of said plurality of sectors.

4. The memory array of claim 1 wherein said at least a portion of said data corresponds to an event and wherein said memory management module is configured to transfer said at least a portion of said data from said random access memory array to said flash memory array when all of said at least a portion of said data corresponding to said event is stored in said random access memory array.

5. The memory array of claim 4 wherein said event is a completion of storage of a predetermined block of data in said random access memory.

6. The memory array of claim 5 wherein said flash memory array comprises a plurality of sectors, at least one of said plurality of sectors having a data storage capacity.

7. The memory array of claim 6 wherein an amount of data of said predetermined block of data is less than said data storage capacity of said at least one of said plurality of sectors.

8. The memory array of claim 6 wherein an amount of data of said predetermined block of data exceeds said data storage capacity of said at least one of said plurality of sectors.

9. The memory array of claim 8 wherein said memory management module is configured to transfer, from said random access memory to said flash memory, a portion of said predetermined block of data equal to said data storage capacity of said at least one of said plurality of sectors.

10. The memory array of claim 6 wherein a plurality of said predetermined blocks of data corresponding to a plurality of storage events are stored in said random access memory, and wherein said memory management module is configured to transfer, from said random access memory to said flash memory, said plurality of said predetermined blocks of data to said flash memory when an amount of said data of said plurality of predetermined blocks of data is at least said data capacity of said at least one of plurality of sectors.

11. A system, comprising:
a memory array for storing data, comprising:
a flash memory array;
a random access memory array operatively coupled to said flash memory, said random access memory and said flash memory configured to receive said data;
a memory management module operatively coupled to said random access memory array and to said flash memory array, said memory management module being configured to transfer at least a portion of said data stored in said random access memory array to said flash memory array; and
a data bus operatively coupled to said flash memory array and configured to output directly said at least a portion of said data in said flash memory array without again storing said output in said random access memory array; and
an external controller operatively coupled to said memory array and having firmware configured to control, at least in part, said memory array, wherein said external controller is configured to:
detect an operation of an implantable medical device; and
upon detecting said operation of the implantable medical device, issue an interrupt command to said memory management module.

12. The system of claim 11 wherein said random access memory array comprises a static random access memory array.

13. The system of claim 11 wherein said flash memory array comprises a plurality of sectors, at least one of said plurality of sectors having a data storage capacity and wherein said memory management module is configured to transfer said at least a portion of said data from said random access memory array to said flash memory array when said at least a portion of said data stored in said random access memory array equals said data storage capacity of said at least one of said plurality of sectors.

14. The system of claim 11 wherein said at least a portion of said data corresponds to an event and wherein said memory management module is configured to transfer said at least a portion of said data from said random access memory array to said flash memory array when all of said at least a portion of said data corresponding to said event is stored in said random access memory array.

15. The system of claim 14 wherein said event is a completion of storage of a predetermined block of data in said random access memory.

16. The system of claim 15 wherein said flash memory array comprises a plurality of sectors, at least one of said plurality of sectors having a data storage capacity.

17. The system of claim 16 wherein an amount of data of said predetermined block of data is less than said data storage capacity of said at least one of said plurality of sectors.

18. The system of claim 16 wherein an amount of data of said predetermined block of data exceeds said data storage capacity of said at least one of said plurality of sectors.

19. The system of claim 18 wherein said memory management module is configured to transfer, from said random access memory to said flash memory, a portion of said predetermined block of data equal to said data storage capacity of said at least one of said plurality of sectors.

20. The system of claim 16 wherein a plurality of said predetermined blocks of data corresponding to a plurality of storage events are stored in said random access memory, and wherein said memory management module is configured to transfer, from said random access memory to said flash memory, said plurality of said predetermined blocks of data to said flash memory when an amount of said data of said plurality of predetermined blocks of data is at least said data capacity of said at least one of plurality of sectors.

21. The system of claim 11 , wherein said interrupt command is a pause command, and wherein said memory management module is configured to pause at least one of said transfer or said output in response to said pause command received from said external controller.

22. The system of claim 11 , wherein said interrupt command is an abort comma

Assignees

• Medtronic Inc

Inventors

• Walsh Kevin K
• Gordon Charles R
• Solheim Paul R
• Reiland Jerry D
• Musto Robert D
• Bigelow Duane R

Classifications

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F3/0668

  adopting a particular infrastructure · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C11/005 Primary

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G06F13/387

  for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system · CPC title