Host and multi-display system including the same

Patent metadata

Field	Value
Publication number	US-10096303-B2
Application number	US-201514713080-A
Country	US
Kind code	B2
Filing date	May 15, 2015
Priority date	Aug 25, 2014
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A system on chip (SoC) for transmitting data packets to a display driver integrated circuit (IC) controlling a plurality of displays is provided. The SoC includes a first register, and a central processing unit (CPU) configured to set first values in the first register to adjust a frame rate of each of the displays. A tearing effect (TE) signal detection circuit is configured to detect a TE signal output from the display driver IC. A data transmission circuit is configured to generate a plurality of frame rate adjustment signals using the detected TE signal and the first values and to control transmission timings of the data packets transmitted to the displays using the frame rate adjustment signals.

First claim

What is claimed is:

1. A system on chip (SoC) for transmitting data packets to a display driver integrated circuit (IC) configured to control a plurality of displays, the system on chip comprising:
a first register;
a central processing unit (CPU) configured to set first values in the first register to adjust a frame rate of each of the displays;
a tearing effect (TE) signal detection circuit configured to detect a TE signal output from the display driver IC and indicating a display status of at least one of the plurality of displays; and
a data transmission circuit configured to generate a plurality of frame rate adjustment signals by adjusting a period of the detected TE signal in response to the first values and to control transmission timings of the data packets transmitted to the displays using the frame rate adjustment signals, respectively.

2. The system on chip of claim 1 ,
wherein the data transmission circuit is configured to sequentially transmit transmission timing-controlled data packets to the display driver IC through a single high-speed serial interface (HSSI), wherein the HSSI is one of a display serial interface (DSI), an embedded DisplayPort (eDP) interface, and a high definition multimedia interface (HDMI).

3. The system on chip of claim 2 ,
wherein the data transmission circuit is configured to sequentially transmit the transmission timing-controlled data packets to the display driver IC in frame units.

4. The system on chip of claim 2 ,
wherein the data transmission circuit is configured to sequentially transmit the transmission timing-controlled data packets to the display driver IC in line units.

5. The system on chip of claim 1 ,
wherein the data transmission circuit is configured to generate the data packets each of which includes an identifier for identifying one of the displays, and
the identifier includes a virtual channel identifier and a data type.

6. The system on chip of claim 1 ,
wherein at least one of the first values is 0.

7. The system on chip of claim 1 , further comprising:
a second register configured to store second values set by the CPU; wherein the data transmission circuit comprises:
a plurality of transmission control circuits configured to control transmission of the detected TE signal in response to the second values, respectively; and
a plurality of frame rate adjustment signal generation circuits configured to respectively generate the frame rate adjustment signals using output signals of the respective transmission control circuits and the first values, respectively.

8. The system on chip of claim 7 ,
wherein the CPU is configured to set the first values in the first register and the second values in the second register when booted.

9. The system on chip of claim 1 , further comprising:
a second register configured to store second values set by the CPU; wherein the data transmission circuit comprises:
a display controller configured to generate the frame rate adjustment signals using the detected TE signal, the first values, and the second values and to adjust transmission timings of data to be displayed on the displays using the frame rate adjustment signals;
a data packetizing circuit configured to generate the data packets, each of which comprises transmission timing-controlled data to be displayed on one of the displays and an identifier for identifying the one of the displays; and
a transmitter configured to sequentially transmit the data packets from the data packetizing circuit to the display driver IC;
wherein the identifier includes a virtual channel identifier and a data type.

10. The system on chip of claim 9 ,
wherein the data packetizing circuit is a mobile industry processor interface (MIPI®) display serial interface (DSI) host, and the transmitter is a MIPI D-PHY.

11. A multi-display system, comprising:
a display driver integrated circuit (IC) configured to control operations of a plurality of displays;
a high-speed serial interface; and
a processor configured to sequentially transmit data packets to the display driver IC through the high-speed serial interface, the processor including:
a first register,
a central processing unit (CPU) configured to set first values in the first register to adjust a frame rate of each of the displays,
a tearing effect (TE) signal detection circuit configured to detect a TE signal output from the display driver IC and indicating a display status of at least one of the plurality of displays, and
a data transmission circuit configured to generate a plurality of frame rate adjustment signals by adjusting a period of the detected TE signal in response to the first values and to control transmission timings of the data packets transmitted to the displays using the frame rate adjustment signals.

12. The multi-display system of claim 11 ,
wherein the high-speed serial interface is one of a mobile industry processor interface (MIPI®) display serial interface (DSI), an embedded DisplayPort (eDP) interface, and a high definition multimedia interface (HDMI).

13. The multi-display system of claim 11 ,
wherein the processor further comprises a second register configured to store second values set by the CPU; and wherein the data transmission circuit comprises:
a plurality of transmission control circuits configured to control transmission of the detected TE signal in response to the second values, respectively; and
a plurality of frame rate adjustment signal generation circuits configured to respectively generate the frame rate adjustment signals using output signals of the respective transmission control circuits and the first values, respectively.

14. The multi-display system of claim 11 ,
wherein the data transmission circuit is configured to generate the data packets each of which comprises an identifier for identifying one of the displays, and
the identifier comprises a virtual channel identifier and a data type.

15. The multi-display system of claim 14 ,
wherein the display driver IC is configured to decode a first identifier included in a first data packet among the data packets received through the high-speed serial interface, identify one of the displays based on a decoding result, and transmit first data included in the first data packet to the identified display.

16. The multi-display system of claim 11 ,
wherein the processor further comprises a second register configured to store second values set by the CPU; wherein the data transmission circuit comprises:
a plurality of transmission control circuits configured to control transmission of the detected TE signal in response to the second values, respectively;
a plurality of frame rate adjustment signal generation circuits configured to respectively generate the frame rate adjustment signals using output signals of the respective transmission control circuits and the first values, respectively; and
a display interface configured to generate the data packets and to control transmission timings of the data packets transmitted to the displays using the frame rate adjustment signals.

17. The multi-display system of claim 16 ,
wherein the display interface is configured to generate the data packets each of which includes data to be displayed on one of the displays and an identifier for identifying the one of the displays and the identifier includes a virtual channel identifier and a data type.

18. The multi-display system of claim 17 ,
wherein the display driver IC is configured to decode the identifier included in each of the data packets, identify

Assignees

• Lee Byung Tak
• Kim Kyoung Man
• Roh Jong Ho
• Samsung Electronics Co Ltd

Inventors

• Lee Byung Tak
• Kim Kyoung Man
• Roh Jong Ho

Classifications

• G06F3/1446

  display composed of modules, e.g. video walls · CPC title

• G09G5/18 Primary

  Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) · CPC title

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title

• G09G5/006

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

• G06F3/1431

  using a single graphics controller · CPC title