Fragment shaders perform vertex shader computations

Patent metadata

Field	Value
Publication number	US-10096079-B2
Application number	US-201414297231-A
Country	US
Kind code	B2
Filing date	Jun 5, 2014
Priority date	Jun 10, 2013
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

Graphics processing may include implementing a vertex shader and a pixel shader with the GPU. Vertex indices output from a vertex shader may be written to a cache. The vertex indices written to the cache may be accessed with the pixel shader and vertex parameter values associated with the vertex indices may be accessed from a memory unit with the pixel shader. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

First claim

What is claimed is:

1. A computer graphics processing method comprising:
writing vertex indices output from a vertex shader to a cache;
accessing the vertex indices written to the cache with a pixel shader; and
accessing raw vertex parameter values associated with the vertex indices from a memory unit with the pixel shader, wherein the raw vertex parameter values have not been processed by the vertex shader, wherein the memory unit is accessible by both a Graphics Processing Unit(GPU) and a Central Processing Unit; and
performing vertex shader computations on the raw vertex parameter values with the pixel shader on a per-pixel basis, wherein the vertex shader computations are performed on a pixel for each vertex of a primitive containing the pixel.

2. The method of claim 1 , wherein the vertex shader computations include manipulating a visual effect of a primitive's vertex in three-dimensional virtual space.

3. The method of claim 1 , further comprising interpolating the raw vertex parameter values with the pixel shader.

4. The method of claim 1 , wherein said accessing the vertex indices includes copying the vertex indices from the cache to a local memory unit of a GPU, and accessing the indices from the local memory unit with the pixel shader.

5. The method of claim 1 , wherein accessing the raw vertex parameter values includes accessing parameter values of all three vertices of a triangle primitive.

6. The method of claim 1 , further comprising, after said accessing the raw vertex parameter values:
performing vertex shader computations on the raw vertex parameter values with the pixel shader;
interpolating the raw vertex parameter values with the pixel shader;
performing pixel shader computations on the interpolated parameter values with the pixel shader.

7. The method of claim 1 , wherein the vertex shader output is limited to vertex position and the vertex indices, and wherein the pixel shader performs any remaining vertex shader computations after said accessing the vertex indices.

8. The method of claim 1 , wherein the raw vertex parameter values are stored in vertex buffers in the memory unit.

9. A graphics processing system comprising:
a graphic processing unit (GPU);
a memory unit; and
a cache;
wherein the system is configured to implement a graphic processing method, the method comprising:
implementing a vertex shader and a pixel shader with the GPU;
writing vertex indices output from a vertex shader to the cache;
accessing the vertex indices written to the cache with the pixel shader; and
accessing raw vertex parameter values associated with the vertex indices from the memory unit with the pixel shader, wherein the raw vertex parameter values have not been processed by the vertex shader, wherein the memory unit is accessible by both a Graphics Processing Unit(GPU) and a Central Processing Unit; and

performing vertex shader computations on the raw vertex parameter values with the pixel shader on a per-pixel basis, wherein the vertex shader computations are performed on a pixel for each vertex of a primitive containing the pixel.

10. The system of claim 9 , wherein the GPU comprises a plurality of compute units and a plurality of local memory units, wherein each of the local memory units are associated with a respective one of the compute units.

11. The system of claim 10 , wherein said accessing the vertex indices includes copying the vertex indices from the cache to the local memory units, and accessing the indices from the local memory units with the pixel shader.

12. The system of claim 9 , wherein the cache is integrated with the GPU.

13. The system of claim 9 , wherein the method further comprises performing vertex shader computations on the raw vertex parameter values with the pixel shader.

14. The system of claim 9 , wherein the method further comprises interpolating the raw vertex parameter values with the pixel shader.

15. The system of claim, 9 , wherein the system is an embedded system, mobile phone, personal computer, tablet computer, portable game device, workstation, or game console.

16. A non-transitory computer readable medium having computer readable instructions embodied therein, the computer readable instructions being configured to implement a graphics processing method when executed, the graphics processing method comprising:
writing vertex indices output from a vertex shader to a cache;
accessing the vertex indices written to the cache with a pixel shader; and
accessing raw vertex parameter values associated with the vertex indices from a memory unit with the pixel shader, wherein the raw vertex parameter values have not been processed by the vertex shader, wherein the memory unit is accessible by both a Graphics Processing Unit(GPU) and a Central Processing Unit; and
performing vertex shader computations on the raw vertex parameter values with the pixel shader on a per-pixel basis, wherein the vertex shader computations are performed on a pixel for each vertex of a primitive containing the pixel.

Assignees

• Sony Interactive Entertainment Inc

Inventors

• Cerny Mark Evan
• Simpson David
• Scanlin Jason

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/005

  General purpose rendering architectures · CPC title

• G06T1/60

  Memory management · CPC title