Multi GPU interconnect techniques

Patent metadata

Field	Value
Publication number	US-10096078-B2
Application number	US-201313966262-A
Country	US
Kind code	B2
Filing date	Aug 13, 2013
Priority date	Aug 13, 2013
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A graphics processing subsystem includes one or more memory devices and two or more graphics processing units (GPU). The graphics processing units each include a memory interface. A first sub-set of the memory interface of the first graphics processing unit communicatively couples the first graphics processing unit to the first memory device. A first sub-set of the memory interface of the second graphics processing unit is connected to a second sub-set of the memory interface of the first graphics processing unit.

First claim

What is claimed is:

1. A device comprising:
a first memory device;
a first graphics processing unit including a memory interface, wherein a first sub-set of the bit width of communication links of the memory interface of the first graphics processing unit communicatively couples the first graphics processing unit to the first memory device; and
a second graphics processing unit including a memory interface, wherein a first sub-set of the bit width of communication links of the memory interface of the second graphics processing unit is connected to a second sub-set of the bit width of the communication links of the memory interface of the first graphics processing unit, wherein the combined bit width of first and second sub-set of the bit width of communication links of the memory interface of the first graphics processing unit is equal to the total bit width of the communication links of the memory interface of the first graphics processing unit.

2. The device of claim 1 , further comprising a second memory device, wherein a second sub-set of the bit width of the communication links of the memory interface of the second graphics processing unit communicatively couples the second graphics processing unit to the second memory device.

3. The device of claim 1 , further comprising a third graphics processing unit including a memory interface, wherein a first sub-set of the bit width of communication links of the memory interface of the third graphics processing unit is connected to a second sub-set of the bit width of the communication links of the memory interface of the second graphics processing unit.

4. The device of claim 3 , further comprising a second memory device, wherein a second sub-set of the bit width of the communication links of the memory interface of the third graphics processing unit communicatively couples the third graphics processing unit to the second memory device.

5. The device of claim 1 , wherein the memory interfaces of the first and second graphics processing units comprise frame buffer interfaces.

6. The device of claim 1 , wherein the first and second graphics processing unit are different graphics processing units.

7. A device comprising:
a plurality of graphics processing units (GPU) each including a memory interface, wherein;
a sub-set of the bit width of the communication links of the memory interface of a first GPU is connected to a corresponding sub-set of the bit width of the communication links of the memory interface of the second GPU;
a sub-set of the bit width of the communication links of the memory interface of an Nth GPU is connected to a corresponding sub-set of the bit width of the communication links of the memory interface of an (N−1)th GPU;
corresponding sub-sets of the bit width of the communication links of the memory interface of the second through (N−1)th GPU are connected to corresponding sub-sets of the bit width of the communication links of the memory interfaces of respective previous and next GPUs; and
another sub-set of the bit width of the communication links of the memory interface of at least one of the plurality of GPUs is connected to a respective memory device, wherein the combined bit width of sub-sets of the communication links of the at least one of the plurality of GPUs is equal to the total bit width of the communication links of the memory interface of the at least one of the plurality of GPUs.

8. The device of claim 7 , wherein another sub-set of the bit width of the communication links of the memory interface of the Nth GPU is connected to another corresponding sub-set of the bit width of the communication links of the memory interface of the first GPU.

9. The device of claim 7 , wherein the plurality of GPUs are all the same GPU.

10. The device of claim 7 , wherein the plurality of GPUs include two or more different GPUs.

11. The device of claim 7 , wherein at least one of the plurality of GPUs is communicatively coupled to one or more central processing units of the device by a peripheral component interface express (PCI-E) bus.

12. The device of claim 7 , wherein each of the plurality of GPUs comprises an integrated circuit (IC) including one or more graphics processing cores.

13. The device of claim 7 , wherein each of the plurality of GPUs comprises a graphics card including one or more GPU integrated circuits (IC), wherein each GPU IC includes one or more graphics processing cores.

14. The device of claim 7 , wherein the memory interfaces comprise a frame buffer interface.

Assignees

• Nvidia Corp

Inventors

• Yan Ming
• Chen Chao

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title