Direct memory access control device for at least one computing unit having a working memory

Patent metadata

Field	Value
Publication number	US-10095643-B2
Application number	US-201715479915-A
Country	US
Kind code	B2
Filing date	Apr 5, 2017
Priority date	Apr 13, 2016
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A direct memory access control device for at least one computing unit includes a terminal for connecting the direct memory access control device to a bus system that connects the computing unit to a working memory, and processing circuitry configured to read out, from a source module connected to the bus system, first data of at least one information block stored at least temporarily in the source module, ascertain a target address in the working memory for the at least one information block as a function of the first data and of configuration information, and transmit the at least one information block from the source module to the target address using a direct memory access by the source module to the working memory.

First claim

What is claimed is:

1. A direct memory access control device for at least one computing unit, the direct memory access control device comprising:
a terminal for connecting the direct memory access control device to a bus system that connects the computing unit to a working memory; and
processing circuitry, wherein the processing circuitry is configured to:
receive, from a source module connected to the bus system, a trigger signal;
read out, from the source module in response to the received trigger signal, first data of at least one information block stored at least temporarily in the source module;
ascertain a target address in the working memory for the at least one information block as a function of the read out first data and of configuration information;
transmit the at least one information block from the source module to the target address, using a direct memory access by the source module to the working memory.

2. The direct memory access control device of claim 1 , wherein the source module includes a communication module.

3. The direct memory access control device of claim 1 , wherein the source module includes a CAN communication module.

4. The direct memory access control device of claim 1 , wherein the source module includes an MCAN communication module.

5. The direct memory access control device of claim 1 , wherein the source module includes a FlexRay communication module.

6. The direct memory access control device of claim 1 , wherein the source module includes an Ethernet communication module.

7. The direct memory access control device of claim 1 , wherein the first data includes metadata of the information block.

8. The direct memory access control device of claim 1 , wherein the information block in the source module characterizes a message received by the source module.

9. The direct memory access control device of claim 1 , wherein the configuration information is localized inside the direct memory access control device.

10. The direct memory access control device of claim 1 , wherein the configuration information is localized outside the direct memory access control device.

11. The direct memory access control device of claim 1 , wherein the processing circuitry is configured to ascertain at least one of a computing unit and a working memory intended for the transmission of the at least one information block.

12. The direct memory access control device of claim 1 , wherein the processing circuitry is configured to ascertain the target address as a function of at least one absolute memory address in the working memory.

13. The direct memory access control device of claim 1 , wherein the processing circuitry is configured to ascertain the target address as a function of at least one relative memory address in the working memory.

14. The direct memory access control device of claim 1 , wherein the processing circuitry is configured to set at least one control bit in the at least one information block.

15. The direct memory access control device of claim 1 , wherein the processing circuitry is configured to trigger an interrupt request at the computing unit.

16. The direct memory access control device of claim 1 , wherein the processing circuitry is configured to trigger an interrupt request at a processor core of the computing unit.

17. An operation method of a direct memory access control device for at least one computing unit, the direct memory access control device having a terminal for connecting the direct memory access control device to a bus system that connects the computing unit to a working memory, the method comprising:
receiving, from a source module connected to the bus system, a trigger signal;
reading out, in response to the received trigger signal, by the direct memory access control device and from the source module, first data of at least one information block stored at least temporarily in the source module;
ascertaining, by the direct memory access control device, a target address in the working memory for the at least one information block as a function of the read out first data and as a function of configuration information; and
transmitting, by the direct memory access control device, the at least one information block from the source module to the target address using a direct memory access from the source module to the working memory.

18. The method of claim 17 , wherein the source module includes a communication module.

19. The method of claim 17 , wherein the first data includes metadata of the information block.

20. The method of claim 17 , wherein the information block in the source module characterizes a message received by the source module.

21. The method of claim 17 , further comprising ascertaining at least one of a computing unit and a working memory intended for the transmission of the at least one information block.

22. The method of claim 17 , wherein the target address is ascertained as a function of at least one of (a) at least one absolute first memory address in the working memory and (b) at least one relative second memory address in the working memory.

23. The method of claim 17 , further comprising at least one of setting at least one control bit in the at least one information block and triggering an interrupt request at the computing unit or at a processor core of the computing unit.

Assignees

• Bosch Gmbh Robert

Inventors

• Becker Eugen
• Aue Axel
• Schlottmann Eckart

Classifications

• G06F12/1081

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title