Memory controller and accessing system utilizing the same

Patent metadata

Field	Value
Publication number	US-10095614-B2
Application number	US-201715816892-A
Country	US
Kind code	B2
Filing date	Nov 17, 2017
Priority date	Apr 3, 2013
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level.

First claim

What is claimed is:

1. A memory controller comprising:
a first transmittal module transmitting data and comprising a specific pin;
a first clock pin receiving a first clock signal, wherein the first transmittal module and the first clock pin constitute an embedded multimedia card (eMMC) interface;
a second transmittal module comprising a receiving pin and a transmittal pin, wherein the receiving pin and the transmittal pin transmit data according to a serial method;
a first control module communicating with an external host via the first transmittal module when a level of the specific pin is at a first level; and
a second control module communicating with the external host via the second transmittal module when the level of the specific pin is at a second level, wherein the first level exceeds the second level, the first control module operates independently of the second control module, and the second control module operates independently of the first control module.

2. The memory controller as claimed in claim 1 , wherein when the first control module communicates with the external host, the second control module does not receive an operation voltage, and when the second control module communicates with the external host, the first control module does not receive the operation voltage.

3. The memory controller as claimed in claim 1 , further comprising:
a detection module generating a control signal according to the level of the specific pin.

4. The memory controller as claimed in claim 3 , further comprising:
a second clock pin receiving a second clock signal, wherein the second transmittal module and the second clock pin constitute a universal flash storage (UFS) interface.

5. The memory controller as claimed in claim 4 , wherein when the level of the specific pin is equal to the first level, the control signal is in a first state and the first control module communicates with the external host via the first transmittal module according to the first clock signal, and when the level of the specific pin is equal to the second level, the control signal is in a second state and the second control module communicates the external host via the second transmittal module according to the second clock signal.

6. The memory controller as claimed in claim 1 , wherein when the first control module communicates with the external host, the second control module does not receive the clock signal, and when the second control module communicates with the external host, the first control module does not receive the clock signal.

7. The memory controller as claimed in claim 6 , further comprising:
a detection module generating a control signal according to the level of the specific pin;
a first switch coupled between the clock pin and the first control module and controlled by the control signal, wherein when the control signal is in a first state, the first switch is turned on to transmit the clock signal to the first control module; and
a second switch coupled between the clock pin and the second control module and controlled by the control signal, wherein when the control signal is in a second state, the second switch is turned on to transmit the clock signal to the second control module,
wherein when the first switch is turned on, the second switch is turned off, and when the second switch is turned on, the first switch is turned off.

8. A memory controller comprising:
a first transmittal module transmitting data;
a specific pin;
a first clock pin receiving a first clock signal, wherein the first transmittal module and the first clock pin constitute an embedded multimedia card (eMMC) interface;
a second transmittal module comprising a receiving pin and a transmittal pin, wherein the receiving pin and the transmittal pin transmit data according to a serial method;
a first control module communicating with an external host via the first transmittal module when a level of the specific pin is at a first level; and
a second control module communicating with the external host via the second transmittal module when the level of the specific pin is at a second level, wherein the first level exceeds the second level, the first control module operates independently of the second control module, and the second control module operates independently of the first control module.

9. The memory controller as claimed in claim 8 , wherein when the first control module communicates with the external host, the second control module does not receive an operation voltage, and when the second control module communicates with the external host, the first control module does not receive the operation voltage.

10. The memory controller as claimed in claim 8 , further comprising:
a detection module generating a control signal according to the level of the specific pin.

11. The memory controller as claimed in claim 10 , further comprising:
a second clock pin receiving a second clock signal, wherein the second transmittal module and the second clock pin constitute a universal flash storage (UFS) interface.

12. The memory controller as claimed in claim 11 , wherein when the level of the specific pin is equal to the first level, the control signal is in a first state and the first control module communicates the external host via the first transmittal module according to the first clock signal, and when the level of the specific pin is equal to the second level, the control signal is in a second state and the second control module communicates the external host via the second transmittal module according to the second clock signal.

13. The memory controller as claimed in claim 8 , wherein when the first control module communicates with the external host, the second control module does not receive the clock signal, and when the second control module communicates with the external host, the first control module does not receive the clock signal.

14. The memory controller as claimed in claim 13 , further comprising:
a detection module generating a control signal according to the level of the specific pin;
a first switch coupled between the clock pin and the first control module and controlled by the control signal, wherein when the control signal is in a first state, the first switch is turned on to transmit the clock signal to the first control module; and
a second switch coupled between the clock pin and the second control module and controlled by the control signal, wherein when the control signal is in a second state, the second switch is turned on to transmit the clock signal to the second control module,
wherein when the first switch is turned on, the second switch is turned off, and when the second switch is turned on, the first switch is turned off.

15. An accessing system comprising:
a memory array storing data;
an external host sending a clock signal; and
a memory controller accessing the memory array according to the clock signal and comprising:
a first transmittal module transmitting data and comprising a specific pin;
a first clock pin receiving a first clock signal, wherein the first transmittal module and the first clock pin constitute an embedded multimedia card (eMMC) interface;
a second transmittal module comprising a receiving pin and a transmittal pin, wherein the receiving pin and the transmittal pin transmit data according to a serial method;
a first control module accessing the memory array and communicating with the external host via a coupling directly through the first transmittal module when a level of the specific pin is at a first level, wherein when the first control module accesses the memory arr

Assignees

• Silicon Motion Inc

Inventors

• Chyan Yu-Wei
• Lin Jiyun-Wei

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• Y02D10/14

  Cross-Sectional Technologies · mapped topic