Memory system and method for improving write performance in a multi-die environment

Patent metadata

Field	Value
Publication number	US-10095412-B2
Application number	US-201514939658-A
Country	US
Kind code	B2
Filing date	Nov 12, 2015
Priority date	Nov 12, 2015
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A memory system and method for improving write performance in a multi-die environment are disclosed. In one embodiment, a memory system is provided comprising a plurality of memory dies and a controller. The controller is configured to determine a programming status of each of the plurality of memory dies and dynamically adjust a maximum peak current limit of the plurality of memory dies based on the programming status of each of the plurality of memory dies. Other embodiments are provided.

First claim

What is claimed is:

1. A memory system comprising:
a plurality of memory dies; and
a controller in communication with the plurality of memory dies, wherein the controller is configured to:
perform the following before and after a program operation of each memory die:
send a broadcast status command to the plurality of memory dies;
receive an indication of programming status from each of the plurality of memory dies in response to the broadcast status command; and
dynamically adjust a maximum peak current limit of the plurality of memory dies based on the indication of programming status received from each of the plurality of memory dies such that memory dies whose programming status is active receive a higher maximum peak limit than those memory dies whose programming status is inactive.

2. The memory system of claim 1 , wherein a new maximum peak current limit for a memory die is contained in an address field in a message sent to the memory die.

3. The memory system of claim 1 , wherein the controller is further configured to dynamically adjust the maximum peak current limit before issuing a next program sequence.

4. The memory system of claim 1 , wherein the controller is further configured to dynamically adjust the maximum peak current limit during an ongoing program sequence.

5. The memory system of claim 1 , wherein the controller is further configured to reset the maximum peak current limit.

6. The memory system of claim 1 , wherein at least one of the plurality of memory dies comprises a three-dimensional memory.

7. The memory system of claim 1 , wherein the memory system is embedded in a host.

8. The memory system of claim 1 , wherein the memory system is removably connected to a host.

9. A method for improving write performance in a multi-die memory system, the method comprising:
performing the following before and after a program operation of each memory die in a memory system comprising a plurality of memory dies, wherein the plurality of memory dies is associated with a current budget:
sending a broadcast status command to the plurality of memory dies;
receiving an indication from each memory die as to whether each memory die is active in response to the broadcast status command; and
allocating current from the current budget only to the memory die(s) that are active, wherein the memory die(s) that are active are allocated more than their pro rata share of the current budget, thereby increasing performance of those memory die(s).

10. The method of claim 9 , wherein at least one of the plurality of memory dies comprises a three-dimensional memory.

11. The method of claim 9 , wherein the memory system is embedded in a host.

12. The method of claim 9 , wherein the memory system is removably connected to a host.

13. A memory system comprising:
a plurality of memory dies;
means for sending a broadcast status command to the plurality of memory dies before and after a program operation of each memory die;
means for receiving indications from the plurality of memory dies in response to the broadcast status command to determine how many of the plurality of memory dies are being programmed; and
means for making on-the-fly adjustments to change programming speeds of the memory dies that are being programmed based on how many of the plurality of memory dies are being programmed.

14. The memory system of claim 13 , wherein the controller is configured to make the on-the-fly adjustments by dynamically increasing or decreasing a maximum peak current limit of the plurality of memory dies based on how many of the plurality of memory dies are being programmed.

15. The memory system of claim 13 , wherein at least one of the plurality of memory dies comprises a three-dimensional memory.

16. The memory system of claim 13 , wherein the memory system is embedded in a host.

17. The memory system of claim 13 , wherein the memory system is removably connected to a host.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Hsu Hua-Ling Cynthia
• Manohar Abhijeet
• Avila Victor
• Kuo Tien-Chien
• Yuh Jong Hak

Classifications

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F1/3225

  of memory devices · CPC title

• G06F12/0866

  for peripheral storage systems, e.g. disk cache · CPC title