Method and apparatus for automatic adaptive voltage control

Patent metadata

Field	Value
Publication number	US-10095302-B2
Application number	US-201615250123-A
Country	US
Kind code	B2
Filing date	Aug 29, 2016
Priority date	Aug 29, 2016
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.

First claim

What is claimed is:

1. A processing device, comprising:
power management circuitry to:
receive a base clock (BCLK) frequency rate to be applied to the processing device;
determine, using a first reference voltage/frequency curve, a voltage to operate the processing device corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device;
determine a difference between a value of the BCLK frequency rate with the reference BCLK frequency rate of the processing device;
in response to a determination that the difference is greater than a threshold, generate a second reference voltage/frequency curve based on the voltage corresponding to the BCLK frequency rate and the reference V/F curve; and
determine, using the second reference voltage/frequency curve, a voltage to operate the processing device corresponding to the BCLK frequency rate.

2. The processing device of claim 1 wherein the power management circuitry to interpolate a plurality of BCLK frequencies of the processing device to generate a signal comprising a phase locked loop (PLL) ratio, wherein the PLL ratio is a ratio of each of a plurality of BCLK frequencies of the processing device with the BCLK frequency rate.

3. The processing device of claim 2 , wherein the PLL ratio is multiplied with the BCLK frequency rate to compute a BCLK frequency of the processing device corresponding to the BCLK frequency rate.

4. The processing device of claim 3 , wherein the voltage is determined at the PLL ratio corresponding to the BCLK frequency.

5. A system-on-a chip (SoC) comprising:
a memory; and
a processing device communicably coupled to the memory, wherein the processing device comprises:
power management circuitry to:
receive a base clock (BCLK) frequency rate to be applied to the processing device;
determine, using a first reference voltage/frequency curve, a voltage to operate the processing device corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device;
determine a difference between a value of the BCLK frequency rate with the reference BCLK frequency rate of the processing device;
in response to a determination that the difference is greater than a threshold, generate a second reference voltage/frequency curve based on the voltage corresponding to the BCLK frequency rate and the reference V/F curve; and
determine, using the second reference voltage/frequency curve, a voltage to operate the processing device corresponding to the BCLK frequency rate.

6. The SoC of claim 5 wherein the power management circuitry to interpolate a plurality of BCLK frequencies of the processing device to generate a signal comprising a phase locked loop (PLL) ratio, wherein the PLL ratio is a ratio of each of a plurality of BCLK frequencies of the processing device with the BCLK frequency rate.

7. The SoC of claim 6 wherein the PLL ratio is multiplied with the BCLK frequency rate to compute a BCLK frequency of the processing device corresponding to the BCLK frequency rate.

8. The SoC of claim 6 , wherein the voltage is determined at the PLL ratio corresponding to a BCLK frequency among the plurality of BCLK frequencies of the processing device.

9. A method comprising:
receiving a base clock (BCLK) frequency rate to be applied to the processing device;
determining, using a first reference voltage/frequency curve, a voltage to operate the processing device corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device;
determining a difference between a value of the BCLK frequency rate with the reference BCLK frequency rate of the processing device;
in response to determining the difference is greater than a threshold, generating a second reference voltage/frequency curve based on the voltage corresponding to the BCLK frequency rate and the reference V/F curve; and
determining, using the second reference voltage/frequency curve, a voltage to operate the processing device corresponding to the BCLK frequency rate.

10. The method of claim 9 further comprising interpolating a plurality of BCLK frequencies of the processing device to generate a signal comprising a phase locked loop (PLL) ratio, wherein the PLL ratio is a ratio of each of a plurality of BCLK frequencies of the processing device with the BCLK frequency rate.

11. The method of claim 10 , wherein the voltage is determined at the PLL ratio corresponding to a BCLK frequency among the plurality of BCLK frequencies of the processing device.

12. A non-transitory machine-readable storage medium including instructions that, when accessed by a processing device, cause the processing device to perform operations comprising:
receiving a base clock (BCLK) frequency rate to be applied to the processing device;
determining, using a first reference voltage/frequency curve, a voltage to operate the processing device corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device;
determining a difference between a value of the BCLK frequency rate with the reference BCLK frequency rate of the processing device;
in response to determining the difference is greater than a threshold, generating a second reference voltage/frequency curve based on the voltage corresponding to the BCLK frequency rate and the reference V/F curve; and
determining, using the second reference voltage/frequency curve, a voltage to operate the processing device corresponding to the BCLK frequency rate.

13. The non-transitory machine-readable storage medium of claim 12 , wherein the operations further comprising interpolating a plurality of BCLK frequencies of the processing device to generate a signal comprising a phase locked loop (PLL) ratio, wherein the PLL ratio is a ratio of each of a plurality of BCLK frequencies of the processing device with the BCLK frequency rate.

14. The non-transitory machine-readable storage medium of claim 13 , wherein the voltage is determined at the PLL ratio corresponding to a BCLK frequency among the plurality of BCLK frequencies of the processing device.

Assignees

• Intel Corp

Inventors

• Gur Ariel
• Ragland Daniel J
• Nathan Ofer
• Shulman Nadav
• Natanzon Esfir

Classifications

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title