Selective etching process for SiGe and doped epitaxial silicon
US-12062571-B2 · Aug 13, 2024 · US
US10094988B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10094988-B2 |
| Application number | US-201213600779-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 31, 2012 |
| Priority date | Aug 31, 2012 |
| Publication date | Oct 9, 2018 |
| Grant date | Oct 9, 2018 |
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The disclosed embodiments relate to an integrated circuit structure and methods of forming them in which photonic devices are formed on the back end of fabricating a CMOS semiconductor structure containing electronic devices. Doped regions associated with the photonic devices are formed using microwave annealing for dopant activation.
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What is claimed as new and desired to be protected by Letters Patent of the United States is: 1. A method for fabricating an integrated structure, the method comprising: fabricating a CMOS structure containing an electronic device over a substrate, wherein the electronic device is formed using a first semiconductor material; fabricating a second semiconductor material over the first semiconductor material; fabricating a buried oxide material between the first semiconductor material and the second semiconductor material, fabricating a photonic device using the second semiconductor material, the photonic device comprising a modulator having associated doped regions and a photodetector; and activating the doped regions with microwave energy such that the doped regions are heated to a temperature in the range of about 200 to about 500 degrees Celsius, wherein the buried oxide material is configured to function as a cladding for the photonic device. 2. The method according to claim 1 , wherein the doped regions are heated to a temperature within the range of about 300 to about 400 degrees Celsius. 3. The method according to claim 1 , wherein the second semiconductor material is thicker than the first semiconductor material in which the electronic device of the CMOS structure is formed. 4. The method according to claim 1 , wherein the buried oxide material has a thickness greater than or equal to 1 micrometer and the second semiconductor material has a thickness greater than or equal to 200 nanometers. 5. The method according to claim 1 , wherein the dopant is heated with microwave energy for at least about five minutes. 6. The method according to claim 5 , wherein the dopant is heated with microwave energy for up to about two hours. 7. The method according to claim 1 , wherein the activating step occurs using microwave at a frequency greater than or equal to about 1.5 GHz and less than or equal to about 8.5 GHz. 8. The method according to claim 1 , wherein the activating step occurs using microwaves at a frequency of about 2.45 GHz and at a power of about 1300 W. 9. The method according to claim 1 , wherein fabricating the photonic device comprises forming a waveguide using the second semiconductor material and a photodetector material in association with the waveguide. 10. The method according to claim 9 , wherein the activating occurs before forming the photodetector material. 11. The method according to claim 9 , wherein the activating occurs after forming the photodetector material. 12. The method according to claim 10 , wherein the photodetector material comprises one of germanium and silicon-germanium. 13. The method according to claim 1 , further comprising forming an electrical connection between a metallization material and the photonic device. 14. The method according to claim 13 , further comprising forming an electrical connection between a metallization material associated with an electronic device in the CMOS structure and a metallization material associated with the photonic device. 15. The method according to claim 1 , wherein the photonic device is fabricated after forming the first semiconductor material over the fabricated CMOS structure.
Thermal treatments, e.g. annealing or sintering · CPC title
characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title
Basic optical elements, e.g. light-guiding paths · CPC title
Modulator · CPC title
Silicon · CPC title
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