Using different TCP/IP stacks with separately allocated resources

US10091125B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10091125-B2
Application numberUS-201414231707-A
CountryUS
Kind codeB2
Filing dateMar 31, 2014
Priority dateMar 31, 2014
Publication dateOct 2, 2018
Grant dateOct 2, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Multiple TCP/IP stack processors on a host. The multiple TCP/IP stack processors are provided independently of TCP/IP stack processors implemented by virtual machines on the host. The TCP/IP stack processors provide multiple different default gateway addresses for use with multiple processes. The default gateway addresses allow a service to communicate across an L3 network. Processes outside of virtual machines that utilize the TCP/IP stack processor on a first host can benefit from using their own gateway, and communicate with their peer process on a second host, regardless of whether the second host is located within the same subnet or a different subnet. The multiple TCP/IP stack processors can use separately allocated resources. Separate TCP/IP stack processors can be provided for each of multiple tenants on the host. Separate loopback interfaces of multiple TCP/IP stack processors can be used to create separate containment for separate sets of processes on a host.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of implementing TCP/IP stacks on an electronic computing device that implements a plurality of TCP/IP stacks, the method comprising: allocating a first amount of memory resources for a first TCP/IP stack for a first process executing on the device outside of any virtual machine; allocating a second amount of memory resources for a second TCP/IP stack for a second process executing outside of any virtual machine, said second amount of resources separate from the first amount of memory resources; implementing the first TCP/IP stack with the first amount of memory resources; and implementing the second TCP/IP stack with the second amount of memory resources, wherein memory resources allocated to a particular TCP/IP stack are not available for use by any other TCP/IP stack. 2. The method of claim 1 , wherein at least one of the first and second processes is a storage process. 3. The method of claim 2 , wherein the storage process is one of a network file system and a virtual storage area network. 4. The method of claim 1 , wherein the first process is a storage process and the second process is a virtual machine migration process. 5. The method of claim 1 , wherein the first amount of memory resources is determined by a configuration file of the first TCP/IP stack and the second amount of memory resources is determined by a configuration file of the second TCP/IP stack. 6. The method of claim 1 , wherein the first amount of memory resources is determined based on resource allocation requirements of a plurality of TCP/IP stacks. 7. The method of claim 6 , wherein the plurality of TCP/IP stacks comprises a plurality of presently implemented TCP/IP stacks. 8. The method of claim 6 , wherein the plurality of TCP/IP stacks comprises a plurality of presently implemented TCP/IP stacks and a plurality of presently unimplemented TCP/IP stacks with known resource allocation requirements. 9. The method of claim 1 , wherein said implementing the first and second TCP/IP stacks is performed by the electronic device automatically during a boot up of the electronic device. 10. A non-transitory machine readable medium storing a program which when executed by at least one processing unit implements a plurality of TCP/IP stacks, outside of any virtual machine, the program comprising sets of instructions for: allocating a first amount of memory resources for a first TCP/IP stack for a first process executing on the device outside of any virtual machine; and allocating a second amount of memory resources for a second TCP/IP stack for a second process executing outside of any virtual machine, said second amount of resources separate from the first amount of memory resources, implementing the first TCP/IP stack with the first amount of memory resources; and implementing the second TCP/IP stack with the second amount of memory resources, wherein memory resources allocated to a particular TCP/IP stack are not available for use by any other TCP/IP stack. 11. The non-transitory machine readable medium of claim 10 , wherein the first and second processes are hypervisor service processes. 12. The non-transitory machine readable medium of claim 10 , the program further comprising a set of instructions for implementing connections with the first amount of memory resources and the second amount of memory resources. 13. The non-transitory machine readable medium of claim 10 , the program further comprising a set of instructions for implementing sockets with the first amount of memory resources and the second amount of memory resources. 14. The non-transitory machine readable medium of claim 10 , wherein the first amount of memory resources is equal to the second amount of memory resources. 15. The non-transitory machine readable medium of claim 10 , wherein the first amount of memory resources is different from the second amount of memory resources. 16. The non-transitory machine readable medium of claim 15 , wherein the first amount of memory resources is determined by a configuration file of the first TCP/IP stack and the second amount of memory resources is determined by a configuration file of the second TCP/IP stack. 17. The non-transitory machine readable medium of claim 15 , wherein the first amount of memory resources is determined based on resource allocation requirements of a plurality of TCP/IP stacks. 18. An electronic device implementing a first service and a second service, the electronic device comprising: at least one processing unit; and a non-transitory machine readable medium storing a program that when executed by the at least one processing units implements a plurality of TCP/IP stacks outside of any virtual machine on the electronic device, the program comprising sets of instructions for: allocating a first amount of memory resources to a first TCP/IP stack executing outside of any virtual machine to process data from the first service into IP packets; allocating a second amount of memory resources separate from the first amount of memory resources to a second TCP/IP stack outside of any virtual machine to process data from the second service into IP packets; implementing the first TCP/IP stack with the first amount of resources to prevent data output operations of the first service from impacting the second amount of resources; and implementing the second TCP/IP stack with the second amount of resources to prevent data operations of the second service from impacting the first amount of resources. 19. The electronic device of claim 18 , wherein the first amount of memory resources comprises a first memory space and the second amount of memory resources comprises a second memory space separate from the first memory space. 20. The electronic device of claim 18 , the program further comprising sets of instructions for implementing connections and sockets with the first amount of memory resources and the second amount of memory resources. 21. The electronic device of claim 18 , wherein the first service and the second service run on a kernel space on the electronic device.

Assignees

Inventors

Classifications

  • Hypervisors; Virtual machine monitors · CPC title

  • H04L47/70Primary

    Admission control; Resource allocation · CPC title

Patent family

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Frequently asked questions

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What does patent US10091125B2 cover?
Multiple TCP/IP stack processors on a host. The multiple TCP/IP stack processors are provided independently of TCP/IP stack processors implemented by virtual machines on the host. The TCP/IP stack processors provide multiple different default gateway addresses for use with multiple processes. The default gateway addresses allow a service to communicate across an L3 network. Processes outside of…
Who is the assignee on this patent?
Nicira Inc
What technology area does this patent fall under?
Primary CPC classification G06F9/45533. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 02 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).