Packaged circuit

Patent metadata

Field	Value
Publication number	US-10090993-B2
Application number	US-201715669765-A
Country	US
Kind code	B2
Filing date	Aug 4, 2017
Priority date	Aug 19, 2016
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A packaged circuit including a digital controller, a port physical layer and a digital coding circuit is provided. The digital controller outputs digital data in parallel via a parallel data channel, and the digital data includes a plurality of data bits. The port physical layer includes a clock generator, and outputs a data signal according to the data bits. The clock generator outputs a clock signal to the digital controller. The digital coding circuit is coupled to the digital controller and the port physical layer, and receives the digital data and the clock signal. The digital coding circuit codes the clock signal to generate a plurality of clock bits, and outputs the clock bits to the port physical layer. The port physical layer converts the clock bits into an output clock and outputs the output clock.

First claim

What is claimed is:

1. A packaged circuit, comprising:
a digital controller, parallel outputting digital data in parallel via a parallel data channel, wherein the digital data comprises a plurality of data bits;
a port physical layer, comprising a clock generator, and outputting a data signal according to the data bits, wherein the clock generator outputs a clock signal to the digital controller; and
a digital coding circuit, coupled between the digital controller and the port physical layer, receiving the digital data and the clock signal, generating a plurality of clock bits, and outputting the clock bits to the port physical layer,
wherein the port physical layer converts the clock bits into an output clock and outputs the output clock,
wherein the port physical layer comprises a first output-port-circuit and a second output-port-circuit, and the digital coding circuit outputs the clock bits to the first output-port-circuit or the second output-port-circuit according to an operating state of the packaged circuit.

2. The packaged circuit according to claim 1 , wherein the digital coding circuit outputs the data bits to the second output-port-circuit when the digital coding circuit outputs the clock bits to the first output-port-circuit.

3. The packaged circuit according to claim 1 , wherein the digital coding circuit outputs the data bits to the first output-port-circuit when the digital coding circuit outputs the clock bits to the second output-port-circuit.

4. The packaged circuit according to claim 1 , wherein the first output-port-circuit comprises:
a first serializer, converting one of the data bits and the clock bits from parallel to series; and
a first port-driving-circuit, coupled to the first serializer, and receiving the data bits or the clock bits in series so as to output the data signal or the output clock.

5. The packaged circuit according to claim 4 , wherein the second output-port-circuit comprises:
a second serializer, converting another one of the data bits and the clock bits from parallel to series; and
a second port-driving-circuit, coupled to the second serializer, and receiving the data bits or the clock bits in series so as to output the data signal or the output clock.

6. The packaged circuit according to claim 1 , wherein the packaged circuit operates in a first operating state of the operating state if the packaged circuit is packaged by a first packaging technique; and wherein the packaged circuit operates in a second operating state if the packaged circuit is packaged by a second packaging technique.

7. The packaged circuit according to claim 6 , wherein the packaged circuit further comprises a die body, and wherein an active surface of the die body packaged by the first packaging technique is facing up, and the active surface of the die body packaged by the second packaging technique is facing down.

8. The packaged circuit according to claim 7 , wherein a frequency of the clock signal is identical to a frequency of the output clock.

9. The packaged circuit according to claim 7 , wherein a frequency of the clock signal is different from a frequency of the output clock.

10. The packaged circuit according to claim 7 , wherein the digital coding circuit outputs the clock bits to a first port-driving-circuit of the port physical layer according to the clock signal when the digital controller generates the digital data according to a first transmission interface standard, and the first port-driving-circuit outputs the output clock in response to the clock bits so that the port physical layer outputs the output clock and the data signal which compatible with the first transmission interface standard,
wherein the digital coding circuit does not generate the clock bits when the digital controller generates the digital data according to a second transmission interface standard, and the first port-driving-circuit of the port physical layer outputs the data signal in response to the data bits so that the port physical layer does not output the output clock but outputs the data signal which compatible with the second transmission interface standard.

11. A packaged circuit, comprising:
a digital controller, outputting digital data in parallel via a parallel data channel, wherein the digital data comprises a plurality of data bits;
a port physical layer, connected to a connector, comprising a clock generator, and outputting a data signal to the connector according to the data bits, wherein the clock generator outputs a clock signal to the digital controller; and
a digital coding circuit, coupled to the digital controller and the port physical layer, receiving the digital data and the clock signal, generating a plurality of clock bits, and outputting the clock bits to the port physical layer,
wherein the port physical layer converts the clock bits into an output clock and outputs the output clock,
wherein the digital coding circuit outputs the clock bits to a first output-port-circuit or a second output-port-circuit of the port physical layer according to a plug-in state of an external connector plugged in the connector.

12. The packaged circuit according to claim 11 , wherein the first output-port-circuit comprises:
a first serializer, converting one of the data bits and the clock bits from parallel to series; and
a first port-driving-circuit, coupled to the first serializer, and receiving the data bits or the clock bits in series so as to output the data signal or the output clock.

13. The packaged circuit according to claim 12 , wherein the second output-port-circuit comprises:
a second serializer, converting another one of the data bits and the clock bits from parallel to series; and
a second port-driving-circuit, coupled to the second serializer, and receiving the data bits or the clock bits in series so as to output the data signal or the output clock.

14. The packaged circuit according to claim 11 , wherein the digital coding circuit detects the plug-in state of the external connector via a configuration channel pin, and wherein the plug-in state comprises a non-flipped plug-in state and a flipped plug-in state.

15. The packaged circuit according to claim 14 , wherein the digital coding circuit outputs the clock bits to the second output-port-circuit when in the non-flipped plug-in state, and the digital coding circuit outputs the data bits to the first output-port-circuit of the port physical layer.

16. The packaged circuit according to claim 15 , wherein the second output-port-circuit outputs the output clock to a first data transmission pin of the connector in response to the clock bits, and the first output-port-circuit outputs the data signal to a second data transmission pin of the connector in response to the data bits.

17. The packaged circuit according to claim 16 , wherein the digital coding circuit outputs the clock bits to the first output-port-circuit when in the flipped plug-in state, and the digital coding circuit outputs the data bits to the second output-port-circuit.

18. The packaged circuit according to claim 17 , wherein the first output-port-circuit outputs the output clock to the second data transmission pin of the connector in response to the clock bits, and the second output-port-circuit outputs the data signal to the first data transmission pin of the connector in response to the data bits.

19. The packaged circuit according to claim 15 , wherein the first data transmission pin is configured on a first connection surface of the connector, and the second data transmission pin

Assignees

• Ali Corp

Inventors

• Nee Hsu-Che
• Chen Chi-Bin
• Cheng Yi-Hsien

Classifications

• H04L7/06

  the synchronisation signals differing from the information signals in amplitude, polarity or frequency {or length} · CPC title

• H04L7/0091 Primary

  Transmitter details · CPC title

• G06F13/4063 Primary

  Device-to-bus coupling · CPC title

• G09G5/006

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

• H04L25/14

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title