Microcontroller with digital delay line analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10090850-B2
Application number	US-201715484965-A
Country	US
Kind code	B2
Filing date	Apr 11, 2017
Priority date	Apr 12, 2016
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

Embodiments of the present disclosure include a microcontroller with a processor, memory, and peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.

First claim

The invention claimed is:

1. A microcontroller comprising:
a processor core;
memory; and
a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC), wherein each differential digital delay line is configured to operate at a speed according to a respective differential current, the ADC comprising:
a plurality of differential digital delay lines;
a first circuit comprising a set of delay elements included in the differential digital delay lines;
a second circuit comprising another set of delay elements included in the differential digital delay lines;
wherein:
the first circuit is configured to generate data representing an analog to digital conversion of an input; and
the second circuit is configured to calibrate a source to the differential digital delay lines; and

a plurality of latches configured to store data representing or based on relative speeds of respective delay elements;
wherein a respective latch is configured to save data from a slower differential digital delay line upon a completion of faster differential digital delay line.

2. The microcontroller of claim 1 , further comprising a current source circuit configured to be adjusted by a value produced by the second circuit.

3. The microcontroller of claim 1 , further comprising a current source circuit configured to mirror reference currents to each of the differential digital delay lines based upon the calibration from the second circuit.

4. The microcontroller of claim 1 , wherein the first circuit is configured to measure a difference between an input voltage and a reference voltage and the second circuit is configured to calibrate the source based upon the measurement between the input voltage and the reference voltage.

5. The microcontroller of claim 1 , further comprising a transconductor configured to convert an input differential voltage to a differential current, wherein the first circuit is configured to measure the differential current and generate data representing the differential voltage.

6. The microcontroller of claim 1 , further comprising a transconductor configured to:
convert an input differential voltage to a differential current; and
accept an input based on the plurality of differential digital delay lines to adjust a voltage-to-current range.

7. The microcontroller of claim 1 , wherein each differential digital delay line includes a chain of current limited buffers.

8. The microcontroller of claim 1 , further comprising a third circuit comprising yet another set of delay elements included in the differential digital delay line, wherein the third circuit is configured to produce data to indicate a degree to which an input to the ADC is out of an input range.

9. A microcontroller comprising:
a processor core;
memory; and
a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC), wherein each differential digital delay line is configured to operate at a speed according to a respective differential current, the ADC comprising:
a plurality of differential digital delay lines;
a first circuit comprising a set of delay elements included in the differential digital delay lines; and
a second circuit comprising another set of delay elements included in the differential digital delay lines;
wherein:
the first circuit is configured to generate data representing an analog to digital conversion of an input; and
the second circuit is configured to produce data to indicate a degree to which an input to the ADC is out of an input range; and

a latch configured to save data from a slower differential digital delay line upon a completion of faster differential digital delay line.

10. The microcontroller of claim 9 , wherein the first circuit is configured to measure a difference between an input voltage and a reference voltage.

11. The microcontroller of claim 9 , further comprising a pulse-width-modulation (PWM) circuit, wherein the processor core is configured to adjust operation of the PWM circuit based upon the degree to which the input to the ADC is out of the input range.

12. The microcontroller of claim 9 , wherein the processor core is further configured to adjust the input range based upon the degree to which the input to the ADC is out of the input range.

13. The microcontroller of claim 9 , further comprising a transconductor configured to convert an input differential voltage to a differential current, wherein the first circuit is configured to measure the differential current and generate data representing the differential voltage.

14. The microcontroller of claim 9 , further comprising a transconductor configured to:
convert an input differential voltage to a differential current; and
accept an input based on the plurality of differential digital delay lines to adjust a voltage-to-current range.

15. The microcontroller of claim 9 , wherein each differential digital delay line includes a chain of current limited buffers.

16. The microcontroller of claim 9 , wherein:
a given differential digital delay line is configured to operate at a speed according to a differential current applied to the given differential digital delay line;
the ADC further comprises a latch; and
the latch is configured to save data from a slower differential digital delay line upon a completion of faster differential digital delay line.

17. The microcontroller of claim 9 , further comprising a third circuit comprising a yet another set of delay elements included in the differential digital delay line, wherein the third circuit is configured to calibrate a source to the differential digital delay lines.

18. A microcontroller comprising:
a processor core;
memory; and
a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC), the ADC comprising:
a plurality of differential digital delay lines;
a first circuit comprising a set of delay elements included in the differential digital delay lines; and
a transconductor configured to:
convert an input differential voltage to a differential current; and
accept an input based on the plurality of differential digital delay lines to adjust a voltage-to-current range; and

a plurality of latches configured to store data representing or based on relative speeds of respective delay elements;
wherein a respective latch is configured to save data from a slower differential digital delay line upon a completion of faster differential digital delay line.

19. The microcontroller of claim 1 , wherein the further comprising a second circuit comprising a yet another set of delay elements included in the differential digital delay line, wherein the second circuit is configured to produce data to indicate a degree to which an input to the ADC is out of an input range.

20. The microcontroller of claim 1 , wherein the latches are configured to store thermometer codes.

Assignees

• Microchip Tech Inc

Inventors

• Kris Bryan
• Deutscher Neil

Classifications

• H03M1/1009

  Calibration · CPC title

• H03M1/1071

  Measuring or testing · CPC title

• H03M1/34 Primary

  Analogue value compared with reference values (H03M1/48 takes precedence) · CPC title

• H03K5/14

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• H03K5/131

  Digitally controlled · CPC title