Direct current (DC) voltage converter operation mode transition

Patent metadata

Field	Value
Publication number	US-10090762-B2
Application number	US-201514831080-A
Country	US
Kind code	B2
Filing date	Aug 20, 2015
Priority date	Aug 22, 2014
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A direct current (DC) voltage converter configured to transition between operation modes is disclosed. A voltage selection circuitry is provided in a DC voltage conversion circuit to control a buck-boost converter that generates a DC output voltage. As opposed to conventional methods of switching the buck-boost converter between a buck mode and a boost mode based on a single switching threshold, the voltage selection circuitry is configured to switch the buck-boost converter between the buck mode and the boost mode based on multiple voltage thresholds. Each of the multiple voltage thresholds defines a respective range for the DC output voltage. By controlling the buck-boost converter based on multiple voltage thresholds, it is possible to provide a smoother transition between the buck mode and the boost mode, thus reducing voltage errors in the DC output voltage and improving reliability of the DC voltage conversion circuit.

First claim

What is claimed is:

1. A direct current (DC) voltage conversion circuit, comprising:
a buck-boost converter configured to generate a DC output voltage based on a DC input voltage provided by a voltage source;
a voltage selection circuitry configured to:
receive a DC voltage feedback indicative of a differential between the DC output voltage and a reference voltage; and
compare the DC voltage feedback against a plurality of voltage thresholds to generate a plurality of voltage selection signals that collectively define a lower boundary and an upper boundary of the DC output voltage; and

a voltage control circuitry configured to control the buck-boost converter to generate the DC output voltage between the lower boundary and the upper boundary defined by the plurality of voltage selection signals.

2. The DC voltage conversion circuit of claim 1 wherein the voltage selection circuitry comprises:
a plurality of comparators each corresponding to a respective voltage threshold among the plurality of voltage thresholds, the plurality of comparators configured to generate a plurality of indication signals by comparing the DC voltage feedback against the plurality of voltage thresholds, respectively; and
a plurality of latch circuitries coupled to the plurality of comparators and configured to generate the plurality of voltage selection signals based on the plurality of indication signals.

3. The DC voltage conversion circuit of claim 2 wherein a number of the plurality of latch circuitries is determined by rounding up to an upper integer of a logarithm base two (log 2 ) of a number of the plurality of comparators.

4. The DC voltage conversion circuit of claim 1 further comprising a voltage tracking circuitry configured to generate the DC voltage feedback by comparing the reference voltage to the DC output voltage received from the buck-boost converter.

5. The DC voltage conversion circuit of claim 1 wherein the voltage selection circuitry comprises:
a first comparator configured to receive and compare the DC voltage feedback against a first voltage threshold to generate a first indication signal;
a second comparator configured to receive and compare the DC voltage feedback against a second voltage threshold higher than the first voltage threshold to generate a second indication signal;
a third comparator configured to receive and compare the DC voltage feedback against a third voltage threshold higher than the second voltage threshold to generate a third indication signal;
a first latch circuitry configured to:
receive an inversion of the first indication signal as a first reset (R) signal;
receive the second indication signal as a first set (S) signal; and
generate a first voltage selection signal; and

a second latch circuitry configured to:
receive an inversion of the second indication signal as a second R signal;
receive the third indication signal as a second S signal; and
generate a second voltage selection signal;

wherein the first voltage selection signal and the second voltage selection signal collectively define the lower boundary and the upper boundary of the DC output voltage.

6. The DC voltage conversion circuit of claim 5 wherein the voltage control circuitry controls the buck-boost converter to output the DC output voltage as a ground voltage when the first voltage selection signal and the second voltage selection signal are both logical zeros.

7. The DC voltage conversion circuit of claim 5 wherein the voltage control circuitry controls the buck-boost converter to output the DC output voltage between a ground voltage and the DC input voltage when the first voltage selection signal and the second voltage selection signal are logical one and logical zero, respectively.

8. The DC voltage conversion circuit of claim 5 wherein the voltage control circuitry controls the buck-boost converter to output the DC output voltage higher than the DC input voltage when the first voltage selection signal and the second voltage selection signal are both logical ones.

9. The DC voltage conversion circuit of claim 8 wherein the voltage control circuitry controls the buck-boost converter to output the DC output voltage that is one and a half times the DC input voltage.

10. The DC voltage conversion circuit of claim 8 wherein the voltage control circuitry controls the buck-boost converter to output the DC output voltage that is two times the DC input voltage.

11. The DC voltage conversion circuit of claim 5 wherein:
the first comparator is further configured to:
generate the first indication signal as logical one if the DC voltage feedback is greater than the first voltage threshold; and
generate the first indication signal as logical zero if the DC voltage feedback is less than or equal to the first voltage threshold;

the second comparator is further configured to:
generate the second indication signal as logical one if the DC voltage feedback is greater than the second voltage threshold; and
generate the second indication signal as logical zero if the DC voltage feedback is greater than the first voltage threshold and less than or equal to the second voltage threshold; and

the third comparator is further configured to:
generate the third indication signal as logical one if the DC voltage feedback is greater than the third voltage threshold; and
generate the third indication signal as logical zero if the DC voltage feedback is greater than the second voltage threshold and less than or equal to the third voltage threshold.

12. The DC voltage conversion circuit of claim 11 wherein:
the first latch circuitry is a first cross-coupled negative-OR (NOR) circuitry configured to output the first voltage selection signal on a first Q output; and
the second latch circuitry is a second cross-coupled NOR circuitry configured to output the second voltage selection signal on a second Q output.

13. The DC voltage conversion circuit of claim 5 wherein:
the first comparator is further configured to:
generate the first indication signal as logical zero if the DC voltage feedback is greater than the first voltage threshold; and
generate the first indication signal as logical one if the DC voltage feedback is less than or equal to the first voltage threshold;

the second comparator is further configured to:
generate the second indication signal as logical zero if the DC voltage feedback is greater than the second voltage threshold; and
generate the second indication signal as logical one if the DC voltage feedback is greater than the first voltage threshold and less than or equal to the second voltage threshold; and

the third comparator is further configured to:
generate the third indication signal as logical zero if the DC voltage feedback is greater than the third voltage threshold; and
generate the third indication signal as logical one if the DC voltage feedback is greater than the second voltage threshold and less than or equal to the third voltage threshold.

14. The DC voltage conversion circuit of claim 13 wherein:
the first latch circuitry is a first cross-coupled negative-AND (NAND) circuitry configured to output the first voltage selection signal on a first Q output; and
the second latch circuitry is a second cross-coupled NAND circuitry configured to output the second voltage selection signal on a second Q output.

15. The DC voltage conversion circuit of claim 5 wherein the first voltage threshold, the second voltage threshold, and the third voltage threshold are one volt (1 V), one and four-tenths volts (1.4 V), and one and eight-tenths volts (1.8 V), respect

Assignees

• Rf Micro Devices Inc
• Qorvo Us Inc

Inventors

• Adeeb Mohammad Ahsanul
• Gorisse Philippe
• Khlat Nadim
• Kay Michael R

Classifications

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M3/1582 Primary

  Buck-boost converters (H02M3/1584 takes precedence) · CPC title