Circuits and methods for antenna-based self-interference cancellation

Patent metadata

Field	Value
Publication number	US-10090585-B2
Application number	US-201615244869-A
Country	US
Kind code	B2
Filing date	Aug 23, 2016
Priority date	Aug 23, 2015
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

Circuits and methods for antenna-based self-interference cancellation are provided. In some embodiments, circuits for antenna-based self-interference cancellation are provided, the circuits comprising: a transmit antenna having a transmit port that receives a transmit signal; a receive antenna having a receive port that is cross-polarized with respect to the transmit port and having an auxiliary port that is co-polarized with respect to the transmit port; and a termination connected to the auxiliary port that reflects a signal received at the auxiliary port as a reflected signal, wherein the reflected signal counters interference caused by the transmit signal at the receive port.

First claim

What is claimed is:

1. A circuit for antenna-based self-interference cancellation, comprising:
a transmit antenna having a transmit port that receives a transmit signal;
a receive antenna having a receive port that is cross-polarized with respect to the transmit port and having an auxiliary port that is co-polarized with respect to the transmit port; and
a termination connected to the auxiliary port that reflects a signal received at the auxiliary port as a reflected signal, wherein the reflected signal counters interference caused by the transmit signal at the receive port.

2. The circuit of claim 1 , wherein the termination is formed from a parallel combination of a resistance, an inductance, and a capacitance.

3. The circuit of claim 2 , wherein the inductance is fixed.

4. The circuit of claim 3 , wherein the inductance is implemented using a transmission line.

5. The circuit of claim 2 , wherein the resistance is implemented using a voltage controlled attenuator.

6. The circuit of claim 2 , wherein the capacitance is implemented using a varactor diode.

7. The circuit of claim 1 , wherein the transmit port, the receive port, and the auxiliary port each have non-zero feed line length.

8. The circuit of claim 1 , wherein a slope of conductance synthesized by the termination over a frequency range is substantially zero.

Assignees

• Dinc Tolga
• Krishnaswamy Harish
• Univ Columbia

Inventors

• Dinc Tolga
• Krishnaswamy Harish

Classifications

• H04W16/14

  Spectrum sharing arrangements {between different networks} · CPC title

• H04B1/06

  Receivers · CPC title

• H01Q1/38 Primary

  formed by a conductive layer on an insulating support {(patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface  H01Q15/142)} · CPC title

• H01Q1/525

  between emitting and receiving antennas · CPC title

• H01Q5/314

  using frequency dependent circuits or components, e.g. trap circuits or capacitors · CPC title