Decoupling capacitor on strain relaxation buffer layer

Patent metadata

Field	Value
Publication number	US-10090307-B2
Application number	US-201615298733-A
Country	US
Kind code	B2
Filing date	Oct 20, 2016
Priority date	Jan 21, 2016
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.

First claim

What is claimed is:

1. A method of forming an electronic device comprising:
providing a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material to provide a strain relaxed buffer region;
forming a tensile strained semiconductor material layer on a first portion of the relaxed region;
forming a compressive strained semiconductor material layer on a second portion of the relaxed region;
forming an n-type semiconductor device on the tensile strained semiconductor material layer and a p-type semiconductor device on the compressive strained semiconductor material layer;
forming a gate structure for the p-type semiconductor device and a gate structure for the n-type semiconductor device; and
forming a trench capacitor in a third portion of the relaxed region underlying at least one of the tensile strained layer and the compressive strained layer and at a depth within the strain relaxed buffer region that is below the n-type semiconductor device and the p-type semiconductor device, wherein a width of the trench capacitor defined by the end to end distance of a node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surf ace of the substrate structure, the node dielectric being a conformal layer on an entirety of a sidewall of a trench containing said trench capacitor, the sidewall providing said width of the trench capacitator that alternates between said at least two width dimensions, wherein the node dielectric extends vertically along a sidewall of an interlevel dielectric to provide that an upper surface of the node dielectric is coplanar with an upper surface of the gate structure for said p-type semiconductor device and the gate structure for said n-type semiconductor device.

2. The method of claim 1 , wherein the relaxed region is formed on a silicon (Si) substrate.

3. The method of claim 1 , wherein the relaxed region comprises a first semiconductor material of silicon and a second semiconductor material of silicon germanium comprising 25% germanium or less, wherein the first and second semiconductor material layer have a thickness of 45 nm or less.

4. The method of claim 1 , wherein the tensile strained semiconductor material layer is a silicon (Si) layer that is present on the second semiconductor material, and the compressive strained semiconductor material is a silicon and germanium containing layer including greater than 25% germanium that is present on the second semiconductor material layer.

5. The method of claim 1 , wherein said forming the trench capacitor in the third portion of the relaxed region comprises:
etching a trench into a portion of the relaxed region that is separate from the portions underlying the n-type and p-type semiconductor devices;
laterally etching one of the first semiconductor material and the second semiconductor material selectively to the other of the first semiconductor material and the second semiconductor material;
forming a first electrode on sidewalls of the first semiconductor material and the second semiconductor material that provide the trench;
depositing a node dielectric layer conformally on the sidewalls of the trench; and
filling at least a portion of the trench with a second electrode.

6. The method of claim 5 , wherein etching the trench comprises an anisotropic etch.

7. The method of claim 5 , wherein the lateral etch comprises H 2 O 2 wet chemical etching.

8. The method of claim 5 , wherein the first electrode is formed using gas phase doping.

9. The method of claim 5 , wherein the node dielectric is a high-k dielectric material deposited using atomic layer deposition.

10. The method of claim 5 , wherein the second electrode is a metal deposited using atomic layer deposition.

11. A method of forming an electronic device comprising:
providing a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material to provide a strain relaxed buffer region;
forming a tensile strained semiconductor on a first side of the relaxed region;
forming a compressive strained semiconductor on a second side of the relaxed region;
forming a n-type semiconductor device and a p-type semiconductor device on an upper surface of the semiconductor substrate;
forming a gate structure for the p-type semiconductor device and a gate structure for the n-type semiconductor device; and
forming a trench capacitor in a third portion of the relaxed region underlying at least one of the tensile strained layer and the compressive strained layer and at a depth within the strain relaxed buffer region that is below n-type semiconductor device and p-type semiconductor devices, wherein a width of the trench capacitor defined by the end to end distance of a node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure, the node dielectric being a conformal layer on an entirety of a sidewall of a trench containing said trench capacitor, the sidewall providing said width of the trench capacitator that alternates between said at least two width dimensions, wherein the node dielectrically extends vertically along a sidewall of an interlevel dielectric to provide that an upper surface of the node dielectric is coplanar with an upper surface of gate structures for semiconductor devices present on the compressive strained semiconductor and the tensile strained semiconductor.

12. The method of claim 11 , wherein the relaxed region is formed on a silicon (Si) substrate.

13. The method of claim 11 , wherein the relaxed region comprises a first semiconductor material of silicon and a second semiconductor material of silicon germanium comprising 25% germanium or less, wherein the first and second semiconductor material layer have a thickness of 45 nm or less.

14. A method of forming an electronic device comprising:
providing a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material to provide a strain relaxed buffer region;
forming an n-type semiconductor device on a tensile strained semiconductor material layer;
forming a p-type semiconductor device on a compressive strained semiconductor material layer;
forming a gate structure for the p-type semiconductor device and a gate structure for the n-type semiconductor device; and
forming a trench capacitor in a third portion of the relaxed region underlying at least one of the tensile strained layer and the compressive strained layer and at a depth within the strain relaxed buffer region that is below the n-type semiconductor device and the p-type semiconductor device, wherein a width of the trench capacitor defined by the end to end distance of a node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure, the node dielectric being a conformal layer on an entirety of a sidewall of a trench containing said trench capacitor, the sidewall providing said width of the trench capacitator that alternates between said at least two width dimensions, wherein the node dielectrically extends vertically along a sidewall of an interlevel dielectric to provide that an upper surface of the node dielectric is coplanar with an upper surface of the gate structure for said p-type semiconductor device and the gate structure for said n-type

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Cheng Kangguo
• Hashemi Pouya
• Reznicek Alexander

Classifications

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H01L29/165

  Electricity · mapped topic