Method including a formation of a diffusion barrier and semiconductor structure including a diffusion barrier

Patent metadata

Field	Value
Publication number	US-10090195-B2
Application number	US-201615257245-A
Country	US
Kind code	B2
Filing date	Sep 6, 2016
Priority date	Oct 21, 2015
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A method includes forming a diffusion barrier over a semiconductor structure. The formation of the diffusion barrier includes performing a first tantalum deposition process, the first tantalum deposition process forming a first tantalum layer over the semiconductor structure, performing a treatment of the first tantalum layer, and performing a second tantalum deposition process after the treatment of the first tantalum layer. The treatment modifies at least a portion of the first tantalum layer. The second tantalum deposition process forms a second tantalum layer over the first tantalum layer.

First claim

What is claimed:

1. A method, comprising:
forming a diffusion barrier over a semiconductor structure, the formation of said diffusion barrier comprising:
performing a first tantalum deposition process, said first tantalum deposition process forming a first tantalum layer over said semiconductor structure, said first tantalum layer having a first proportion of alpha tantalum;
performing a treatment to modify said first tantalum layer, wherein said treatment amorphizes at least a portion of said first tantalum layer; and
after said treatment of said first tantalum layer, performing a second tantalum deposition process, said second tantalum deposition process forming a second tantalum layer over said modified first tantalum layer, wherein said second tantalum layer has a second proportion of alpha tantalum that is greater than said first proportion of alpha tantalum in said first tantalum layer.

2. The method of claim 1 , wherein modifying said first tantalum layer induces a formation of an alpha phase of tantalum in at least a portion of at least said second tantalum layer.

3. The method of claim 1 , wherein performing said treatment of said first tantalum layer comprises exposing said first tantalum layer to a plasma comprising at least one of nitrogen, a chemical compound comprising nitrogen, and argon.

4. The method of claim 3 , wherein said plasma is substantially a nitrogen plasma.

5. The method of claim 3 , wherein said plasma is an inductively coupled plasma.

6. The method of claim 1 , wherein said treatment of said first tantalum layer is performed in situ.

7. The method of claim 1 , wherein said semiconductor structure comprises at least one of a contact via and a trench provided in an interlayer dielectric, and wherein said diffusion barrier covers a bottom surface and sidewall surfaces of said at least one of said contact via and said trench.

8. The method of claim 7 , further comprising, after the formation of said diffusion barrier, forming a seed layer over said diffusion barrier and filling said at least one of said contact via and said trench with an electrically conductive material.

9. The method of claim 1 , wherein the formation of said diffusion barrier further comprises, before performing said first tantalum deposition process, forming a tantalum nitride layer over said semiconductor structure, said first tantalum layer being formed over said tantalum nitride layer.

10. A method, comprising:
forming a diffusion barrier over a semiconductor structure, the formation of said diffusion barrier comprising:
depositing a first tantalum nitride layer over said semiconductor structure, the deposition of said first tantalum nitride layer comprising performing a physical vapor deposition process that deposits tantalum nitride;
depositing a second tantalum nitride layer over said first tantalum nitride layer, the deposition of said second tantalum nitride layer comprising performing an atomic layer deposition process that deposits tantalum nitride, wherein a nitrogen content of said second tantalum nitride layer is greater than a nitrogen content of said first tantalum nitride layer; and
depositing a first tantalum layer over said second tantalum nitride layer.

11. The method of claim 10 , wherein at least a portion of said first tantalum layer comprises an alpha phase of tantalum.

12. The method of claim 10 , wherein said atomic layer deposition process includes at least one of a thermal atomic layer deposition process and a plasma enhanced atomic layer deposition process.

13. The method of claim 10 , further comprising depositing a second tantalum layer over said first tantalum nitride layer, wherein said second tantalum nitride layer is deposited over said second tantalum layer.

14. The method of claim 10 , wherein said first tantalum nitride layer is deposited directly on said second tantalum nitride layer.

15. The method of claim 10 , wherein said semiconductor structure comprises at least one of a contact via and a trench formed in an interlayer dielectric, said diffusion barrier covering a bottom surface and sidewall surfaces of said at least one of said contact via and said trench, the method further comprising:
forming a seed layer over said diffusion barrier; and
performing an electroplating process to fill said at least one of said contact via and said trench with an electrically conductive material.

16. A method, comprising:
forming a diffusion barrier over a semiconductor structure, wherein forming said diffusion barrier comprises:
depositing a first tantalum layer over said semiconductor structure, said first tantalum layer having a first proportion of alpha tantalum;
performing a treatment of said first tantalum layer, wherein performing said treatment comprises modifying at least a portion of said first tantalum layer by exposing said first tantalum layer to a flow of a substantially non-ionized gas comprising nitrogen; and
after performing said treatment of said first tantalum layer, depositing a second tantalum layer over said modified first tantalum layer, wherein said at least said modified portion of said first tantalum layer induces a formation of an alpha phase of tantalum in at least a portion of at least said second tantalum layer, said second tantalum layer having a second proportion of alpha tantalum that is greater than said first proportion of alpha tantalum in said first tantalum layer.

17. The method of claim 16 , wherein forming said diffusion barrier further comprises depositing a tantalum nitride layer over said semiconductor structure prior to depositing said first tantalum layer, said first tantalum layer being deposited over said tantalum nitride layer.

18. The method of claim 16 , wherein said treatment of said first tantalum layer is performed in situ.

19. The method of claim 16 , wherein said semiconductor structure comprises at least one of a contact via and a trench formed in an interlayer dielectric, said diffusion barrier covering a bottom surface and sidewall surfaces of said at least one of said contact via and said trench.

20. The method of claim 19 , further comprising forming a seed layer over said diffusion barrier and filling said at least one of said contact via and said trench with an electrically conductive material.

Assignees

• Globalfoundries Inc

Inventors

• Koschinsky Frank
• Hintze Bernd
• Weber Heiko

Classifications

• H10P14/432

  using selective deposition · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title