System for testing charge trap memory cells

Patent metadata

Field	Value
Publication number	US-10090063-B2
Application number	US-201715427136-A
Country	US
Kind code	B2
Filing date	Feb 8, 2017
Priority date	Dec 9, 2015
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A circuit for testing a memory includes a complementary charge trap memory cell, which includes a first transistor and a second transistor. A logical value of the cell corresponds to respective states of the first transistor and the second transistor. The circuit further includes a first bitline coupled to the first transistor, where the first transistor is configured to apply a first voltage to the first bitline. The circuit includes a second bitline coupled to the second transistor, where the second transistor is configured to apply a second voltage to the second bitline. The circuit also includes a sense circuit configured to output, prior to programming of the complementary charge trap memory cell, a logical high signal or a logical low signal in response to the first voltage on the first bitline and the second voltage on the second bitline.

First claim

The invention claimed is:

1. A non-transitory computer-readable storage device storing computer-executable instructions, that when executed by at least one processor, cause the at least one processor to perform operations comprising:
applying a first voltage to a first bitline via a first transistor of a charge trap memory cell, wherein the first transistor is directly coupled to a first power source;
applying a second voltage to a second bitline via a second transistor of the charge trap memory cell, wherein the second transistor is directly coupled to a second power source; and
outputting, prior to programming of the charge trap memory cell, a logical high signal or a logical low signal in response to applying the first voltage to the first bitline and the second voltage to the second bitline.

2. The non-transitory computer-readable storage device of claim 1 , further comprising applying, in response to a programming indication, a third voltage to the first bitline and to the second bitline to program one or more cells of the charge trap memory cell.

3. The non-transitory computer-readable storage device of claim 1 , further comprising receiving a test configuration indication, wherein the first voltage is applied to the first bitline and the second voltage is applied to the second bitline in response to receiving the test configuration indication.

4. The non-transitory computer-readable storage device of claim 1 , further comprising:
pulling the second bitline toward a ground voltage in response to a first bitline voltage corresponding to the first bitline satisfying a first voltage threshold; and
pulling the first bitline toward the ground voltage in response to a second bitline voltage corresponding to the second bitline satisfying a second voltage threshold.

5. The non-transitory computer-readable storage device of claim 1 , further comprising:
pulling the first bitline toward a ground voltage prior to the first transistor applying the first voltage to the first bitline; and
pulling the second bitline toward the ground voltage prior to the second transistor applying the second voltage to the second bitline.

6. The non-transitory computer-readable storage device of claim 1 , wherein the first transistor applies the first voltage to the first bitline in response to a test configuration indication.

7. The non-transitory computer-readable storage device of claim 6 , wherein the second transistor applies the second voltage to the second bitline in response to the test configuration indication.

8. The non-transitory computer-readable storage device of claim 1 , further comprising using a third transistor to pull the second bitline toward a ground voltage in response to a first bitline voltage corresponding to the first bitline satisfying a first voltage threshold.

9. The non-transitory computer-readable storage device of claim 8 , further comprising using a fourth transistor to pull the first bitline toward the ground voltage in response to a second bitline voltage corresponding to the second bitline satisfying a second voltage threshold.

10. The non-transitory computer-readable storage device of claim 1 , wherein the first transistor and the second transistor are field effect transistors.

11. The non-transitory computer-readable storage device of claim 1 , further comprising coupling the first bitline to the first power supply.

12. The non-transitory computer-readable storage device of claim 11 , further comprising coupling the second bitline to the second power supply.

13. The non-transitory computer-readable storage device of claim 1 , further comprising using a third transistor to pull the first bitline toward a ground voltage prior to the first transistor applying the first voltage to the first bitline.

14. The non-transitory computer-readable storage device of claim 13 , further comprising using a fourth transistor to pull the second bitline toward the ground voltage prior to the second transistor applying the second voltage to the second bitline.

15. The non-transitory computer-readable storage device of claim 1 , further comprising coupling a first inverter to the first bitline.

16. The non-transitory computer-readable storage device of claim 15 , further comprising coupling a third transistor to an output of the first inverter.

17. The non-transitory computer-readable storage device of claim 16 , further comprising a third transistor to pull the first bitline up to a supply voltage in response to the output of the first inverter satisfying a first voltage threshold associated with the third transistor.

18. The non-transitory computer-readable storage device of claim 1 , further comprising coupling a second inverter to the second bitline.

19. The non-transitory computer-readable storage device of claim 18 , further comprising pulling the second bitline up to a supply voltage in response to an output of the second inverter satisfying a voltage threshold.

20. The non-transitory computer-readable storage device of claim 1 , further comprising further comprising receiving a test configuration indication, wherein the first voltage is applied to the first bitline and the second voltage is applied to the second bitline in response to receiving the test configuration indication.

Assignees

• IBM

Inventors

• Erickson Karl R
• Paone Phil C
• Paulsen David P
• Sheets Ii John E
• Uhlmann Gregory J

Classifications

• G11C2029/1202

  Word line control · CPC title

• G11C2029/1204

  Bit line control · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C2029/5004

  Voltage · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title