Discharging electric charge in integrated circuit unless in-specification condition(s) detected

Patent metadata

Field	Value
Publication number	US-10090025-B2
Application number	US-201615292616-A
Country	US
Kind code	B2
Filing date	Oct 13, 2016
Priority date	Oct 13, 2016
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

In one embodiment, an integrated circuit comprises a volatile memory including a plurality of memory cells, a detector to detect one or more in-specification conditions, and a discharger, external to the volatile memory, to discharge electric charge stored in the integrated circuit, including electric charge stored in the volatile memory, unless the detector detects the one or more conditions.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a volatile memory including a plurality of memory cells;
a detector, external to the volatile memory, to detect one or more in-specification conditions; and
a discharger, external to the volatile memory, to discharge electric charge stored in the integrated circuit, including electric charge stored in the volatile memory, unless the detector detects said one or more in-specification conditions.

2. The integrated circuit of claim 1 , wherein said discharger includes at least one p-mos or bipolar PNP transistor,
wherein: a source and a drain of each of the at least one p-mos transistor are connected to the volatile memory and a gate of each of the at least one p-mos transistor is coupled to the detector; or
an emitter and a collector of each of the at least one bipolar PNP transistor are connected to the volatile memory and a base of each of the at least one bipolar PNP transistor is coupled to the detector.

3. The integrated circuit of claim 1 , wherein said discharger includes at least one n-mos or bipolar NPN transistor,
wherein: a source and a drain of each of the at least one n-mos transistor are connected to the volatile memory, and a gate of each of the at least one n-mos transistor is coupled to the detector via a gate that is powered by a voltage that is also powering the volatile memory; or
an emitter and a collector of each of the at least one bipolar PNP transistor are connected to the volatile memory and a base of each of the at least one bipolar PNP transistor is coupled to the detector via a gate that is powered by a voltage that is also powering the volatile memory.

4. The integrated circuit of claim 1 , wherein said one or more in-specification conditions includes that for each of at least one parameter, the parameter is within a predetermined range that includes a nominal value of the parameter for the integrated circuit.

5. The integrated circuit of claim 4 , wherein said at least one parameter includes a voltage supplied to the integrated circuit.

6. The integrated circuit of claim 4 , wherein said at least one parameter includes one or more selected from a group comprising: temperature, clock rate, power, voltage, voltage difference, light absorption, radiation absorption, or current.

7. The integrated circuit of claim 1 , wherein said discharger is operative to discharge if said detector does not detect at least one of said one or more in-specification conditions due to at least one of:
for at least one parameter, the parameter is not within a predetermined range including a nominal value of the parameter for the integrated circuit; or
no power or insufficient power to perform detection is provided to the detector.

8. The integrated circuit of claim 1 , further comprising a charger operative to provide a positive voltage for powering the volatile memory only if a power source that is external to the integrated circuit is supplying power to the integrated circuit and the detector detects said one or more in-specification conditions.

9. The integrated circuit of claim 8 , wherein said charger is a power regulator or a switch.

10. The integrated circuit of claim 8 wherein said charger includes at least one n-mos or bipolar NPN transistor.

11. The integrated circuit of claim 10 , wherein:
a gate of each of said at least one n-mos transistor is coupled to the detector, and a source of each of said at least one n-mos is connected to the volatile memory; or
a base of each of said at least one bipolar NPN transistor is coupled to the detector, and an emitter of each of said at least bipolar NPN transistor is coupled to the volatile memory.

12. The integrated circuit of claim 1 , wherein said plurality of memory cells includes memory cells of different types.

13. The integrated circuit of claim 1 , wherein said integrated circuit is or includes a microcontroller.

14. A system comprising an integrated circuit, the integrated circuit including:
a volatile memory including a plurality of memory cells;
a detector that is in the integrated circuit but external to the volatile memory to detect one or more in-specification conditions; and
a discharger that is in the integrated circuit but external to the volatile memory to discharge electric charge stored in the integrated circuit, including electric charge stored in the volatile memory, unless the detector detects said one or more in-specification conditions.

15. The system of claim 14 , wherein said system is a smart card, a memory device, or a computer.

16. The system of claim 14 , wherein said system includes a smart card that includes the integrated circuit, said system further comprising a reader configured to provide power to the smart card.

17. A method of protecting data in volatile memory that includes a plurality of memory cells in an integrated circuit, the method comprising:
determining that at least one of one or more in-specification conditions is not detected by a detector that is in the integrated circuit but external to the volatile memory; and
based on said determining, discharging electric charge stored in the integrated circuit, including electric charge stored in the volatile memory by a discharger that is in the integrated circuit but external to the volatile memory.

18. The method of claim 17 , further comprising:
based on said determining, not providing power to the volatile memory by a charger.

19. The method of claim 17 , wherein said at least one in-specification condition is not detected due to at least one of:
for at least one parameter, the parameter is not within a predetermined range that includes a nominal value of the parameter for the integrated circuit, or
no power or insufficient power to perform detection is provided.

20. The method of claim 17 , wherein the discharging causes a voltage across the volatile memory to be reduced.

Assignees

• Cisco Tech Inc

Inventors

• Elbaum Reuven

Classifications

• G11C16/22

  Safety or protection circuits preventing unauthorised or accidental access to memory cells · CPC title

• G11C5/148 Primary

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C7/24

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title