Gate driver on array unit, related gate driver on array circuit, display device containing the same, and method for driving the same

Patent metadata

Field	Value
Publication number	US-10089948-B2
Application number	US-201615529613-A
Country	US
Kind code	B2
Filing date	Dec 12, 2016
Priority date	Mar 30, 2016
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

The present application discloses a gate driver on array (GOA) unit, including: a buffering module, a pull-up module, a pull-down module, a retaining module, a charging module, and a discharging module, a pull-up node being coupled to the buffering module, the discharging module, the pull-up module, and the charging module, and a pull-down node being coupled to the discharging module and the retaining module. The buffering module, being coupled to an input signal terminal and a pull-up node and controlled by a voltage of the input signal terminal, is configured to output the voltage of the input signal terminal into the pull-up node. The pull-up module, being coupled to a first clock signal terminal, the pull-up node, and an output signal terminal and controlled by a voltage of the pull-up node, is configured to output a voltage of the first clock signal terminal into the output signal terminal.

First claim

What is claimed is:

1. A gate driver on array (GOA) unit, comprising: a buffering module, a pull-up module, a pull-down module, a retaining module, a charging module, and a discharging module, a pull-up node being coupled to the buffering module, the discharging module, the pull-up module, and the charging module, and a pull-down node being coupled to the discharging module and the retaining module, wherein: the buffering module, being coupled to an input signal terminal and a pull-up node and controlled by a voltage of the input signal terminal, is configured to output the voltage of the input signal terminal into the pull-up node; the pull-up module, being coupled to a first clock signal terminal, the pull-up node, and an output signal terminal and controlled by a voltage of the pull-up node, is configured to output a voltage of the first clock signal terminal into the output signal terminal; the pull-down module, being coupled to the output signal terminal, a reset signal terminal, and a power signal terminal and controlled by a voltage of the reset signal terminal, is configured to output a voltage of the power signal terminal into the output signal terminal; the retaining module, being coupled to the first clock signal terminal, the power signal terminal, the pull-up node, the pull-down node, and a second clock signal terminal and controlled by a voltage of the second clock signal terminal, is configured to output the voltage of the second clock signal terminal into the pull-down node or write a voltage of the first clock signal terminal into the pull-down node; the charging module, being coupled to the pull-up node and the output signal terminal, is configured to store voltages of the pull-up node and the output signal terminal; the discharging module, being coupled to the reset signal terminal, the pull-up node, the power signal terminal, the pull-down node, and the output signal terminal, is configured to output the voltage of the power signal terminal into the pull-up node or into the output signal terminal when the discharging module is controlled by voltages of the pull-down node and the reset signal terminal, and configured to write the voltage of the power signal terminal into the pull-up node and the output signal terminal when the discharging module is controlled by the voltage of the pull-down node; and wherein: the retaining module further includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a diode, the first transistor having a first electrode coupled to the second clock signal terminal, a second electrode of the first transistor coupled to a switch electrode of the second transistor, a switch electrode of the fifth transistor, and a second electrode of the fourth transistor, and a switch electrode of the first transistor coupled to the second clock signal terminal; the second transistor having a first electrode coupled to the second clock signal terminal, a second electrode coupled to the pull-down node; the third transistor having a first electrode coupled to the power signal terminal, a second electrode coupled to the pull-down node, and a switch electrode coupled to the pull-up node and a switch electrode of the fourth transistor; the fourth transistor having a first electrode coupled to the power signal terminal; the fifth transistor having a first electrode coupled to a cathode of the diode, and a second electrode coupled to the pull-down node; and the diode having an anode coupled to the first clock signal terminal.

2. The GOA unit according to claim 1 , wherein: the buffering module further includes a sixth transistor,
the sixth transistor having a first electrode coupled to the input signal terminal, a second electrode coupled to the pull-up node, and a switch electrode coupled to the input signal terminal.

3. The GOA unit according to claim 1 , wherein: the pull-up module includes a seventh transistor,
the seventh transistor having a first electrode coupled to the first clock signal terminal, a second electrode coupled to the output signal terminal, and a switch electrode coupled to the pull-up node.

4. The GOA unit according to claim 3 , wherein: the pull-down module includes an eighth transistor,
the eighth transistor having a first electrode coupled to the power signal terminal, a second electrode coupled to the output signal terminal, and a switch electrode coupled to the reset signal terminal.

5. The GOA unit according to claim 1 , wherein: the charging module includes a capacitor,
the capacitor having a terminal coupled to the pull-up node, and another terminal coupled to the output signal terminal.

6. The GOA unit according to claim 1 , wherein: the discharging module includes a ninth transistor, a tenth transistor, and an eleventh transistor,
the ninth transistor having a first electrode coupled to the power signal terminal, a second electrode coupled to the pull-up node, and a switch electrode coupled to the reset signal terminal;
the tenth transistor having a first electrode coupled to the power signal terminal, a second electrode coupled to the pull-up node, and a switch electrode coupled to the pull-down node; and
the eleventh transistor having a first electrode coupled to the power signal terminal, a second electrode coupled to the output signal terminal, and a switch electrode coupled to the pull-down node.

7. The GOA unit according to claim 1 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor are N-type transistors.

8. The GOA unit according to claim 7 , wherein the first electrode of any of the transistors is a source electrode, the second electrode of any of the transistors is a drain electrode, and the switch electrode of any of the transistors is a gate electrode.

9. A method for driving a GOA unit according to claim 1 , comprising implementing a pull-down stage and a retaining stage, wherein,
the pull-down stage including:
applying a first-level voltage on the first clock signal terminal, the input signal terminal, and the power signal terminal;
applying a second-level voltage on the second clock signal terminal and the reset signal terminal;
applying the second-level voltage on a terminal of the discharging module coupled to the retaining module, and
applying the first-level voltage on the output signal terminal; and
the retaining stage including:
applying the first-level voltage on the second clock signal terminal, the input signal terminal, the reset signal terminal, and the power signal terminal;
applying the second-level voltage on the first clock signal terminal;
applying the second-level voltage on the pull-down node; and
applying the first-level voltage of the power signal terminal on the pull-up node and the output signal terminal.

10. The method according to claim 9 , wherein the first-level voltage is a voltage of low voltage level and the second-level voltage is a voltage of high voltage level.

11. The method according to claim 10 , the retaining module including the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the diode; the buffering module including the sixth transistor; the pull-up module including the seventh transistor; the pull-down module including the eighth transistor; the charging module including the capacitor; the discharging module including the ninth transistor, the tenth transistor, and the eleventh transistor, wherein:
in the pull-down stage, the first-level voltage is applied

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Gao Yingqiang
• Chen Huabin
• Wang Dongliang
• Cui Xiaopeng

Classifications

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G3/36

  using liquid crystals · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2320/0219

  Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title