Gate driving circuit controlling a plurality of transistors with one Q node and display device using the same

Patent metadata

Field	Value
Publication number	US-10089915-B2
Application number	US-201615148265-A
Country	US
Kind code	B2
Filing date	May 6, 2016
Priority date	Jun 24, 2015
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A gate driving circuit and a display device using the same are provided. The gate driving circuit includes a first gate driving circuit configured to sequentially generate first and second output voltages and a second gate driving circuit configured to sequentially generate first and second output voltages. The first gate driving circuit and the second gate driving circuit are asymmetrically connected to gate lines. The first output voltage of the first gate driving circuit is supplied to an nth gate line, and the second output voltage of the second gate driving circuit is supplied to the nth gate line.

First claim

What is claimed is:

1. A gate driving circuit, comprising:
a first gate driving circuit configured to sequentially generate first and second output voltages; and
a second gate driving circuit configured to sequentially generate first and second output voltages,
wherein the first gate driving circuit and the second gate driving circuit are asymmetrically connected to gate lines,
wherein the first output voltage of the first gate driving circuit is supplied to an nth gate line, where n is a positive integer, and the second output voltage of the second gate driving circuit is supplied to the nth gate line,
wherein the first gate driving circuit includes first and second pull-up transistors that are connected to one end of the nth gate line and one end of an (n+1)th gate line and successively charge the nth gate line and the (n+1)th gate line under the control of a first Q node, and
wherein the second gate driving circuit includes third and fourth pull-up transistors that are connected to the other end of an (n−1)th gate line and the other end of the nth gate line and successively charge the (n−1)th gate line and the nth gate line under the control of a second Q node.

2. The gate driving circuit of claim 1 , wherein the first output voltage of the first gate driving circuit is supplied to the nth gate line through the first pull-up transistor when the first Q node is firstly bootstrapped in response to an nth clock,
wherein the second output voltage of the first gate driving circuit is supplied to the (n+1)th gate line through the second pull-up transistor when the first Q node is secondly bootstrapped in response to an (n+1)th clock,
wherein the first output voltage of the second gate driving circuit is supplied to the (n−1)th gate line through the third pull-up transistor when the second Q node is firstly bootstrapped in response to an (n−1)th clock, and
wherein the second output voltage of the second gate driving circuit is supplied to the nth gate line through the fourth pull-up transistor when the second Q node is secondly bootstrapped in response to the nth clock.

3. The gate driving circuit of claim 2 , wherein each of the first and second gate driving circuits generates dummy outputs through a dummy stage disconnected from the gate lines, and
wherein a number of dummy outputs of the first gate driving circuit is different from a number of dummy outputs of the second gate driving circuit.

4. The gate driving circuit of claim 1 , wherein a rising time and a falling time of the first output voltage of the first gate driving circuit are different from a rising time and a falling time of the second output voltage of the first gate driving circuit, and
wherein a rising time and a falling time of the first output voltage of the second gate driving circuit are different from a rising time and a falling time of the second output voltage of the second gate driving circuit.

5. A display device, comprising:
a display panel including data lines and gate lines;
a data driving circuit configured to supply a data signal to the data lines;
a first gate driving circuit connected to one end of the respective gate lines and configured to sequentially supply first and second output voltages to the gate lines; and
a second gate driving circuit connected to the other end of the respective gate lines and configured to sequentially supply first and second output voltages to the gate lines,
wherein the first gate driving circuit and the second gate driving circuit are asymmetrically connected to the gate lines,
wherein the first output voltage of the first gate driving circuit is supplied to an nth gate line, where n is a positive integer, and the second output voltage of the second gate driving circuit is supplied to the nth gate line,
wherein the first gate driving circuit includes first and second pull-up transistors that are connected to one end of the nth gate line and one end of an (n+1)th gate line and successively charge the nth gate line and the (n+1)th gate line under the control of a first Q node, and
wherein the second gate driving circuit includes third and fourth pull-up transistors that are connected to the other end of an (n−1)th gate line and the other end of the nth gate line and successively charge the (n−1)th gate line and the nth gate line under the control of a second Q node.

6. The display device of claim 5 , wherein the first output voltage of the first gate driving circuit is supplied to the nth gate line through the first pull-up transistor when the first Q node is firstly bootstrapped in response to an nth clock,
wherein the second output voltage of the first gate driving circuit is supplied to the (n+1)th gate line through the second pull-up transistor when the first Q node is secondly bootstrapped in response to an (n+1)th clock,
wherein the first output voltage of the second gate driving circuit is supplied to the (n−1)th gate line through the third pull-up transistor when the second Q node is firstly bootstrapped in response to an (n−1)th clock, and
wherein the second output voltage of the second gate driving circuit is supplied to the nth gate line through the fourth pull-up transistor when the second Q node is secondly bootstrapped in response to the nth clock.

7. A gate driving circuit, comprising:
a first pull-up transistor configured to drive a first gate line in response to a first Q node voltage;
a second pull-up transistor configured to drive a second gate line in response to the first Q node voltage;
a third pull-up transistor configured to drive the second gate line in response to a second Q node voltage;
a fourth pull-up transistor configured to drive a third gate line in response to the second Q node voltage;
wherein the first Q node voltage is firstly bootstrapped when a first clock is applied to the first pull-up transistor and then is secondly bootstrapped when a second clock is applied to the second pull-up transistor, and
wherein the second Q node voltage is firstly bootstrapped when the second clock is applied to the third pull-up transistor and then is secondly bootstrapped when a third clock is applied to the fourth pull-up transistor.

Assignees

• Lg Display Co Ltd

Inventors

• KIM Haye
• Lee Seeung
• Jeong Seonghun

Classifications

• G09G3/3659

  the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes · CPC title

• G09G2310/0262

  The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title